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BCHG
Explanation of Example: Prior to execution, the 24-bit X location X:$FFE2 (I/O port B
data direction register) contains the value $000000. The execution of the BCHG
#$7,X:<<$FFE2 instruction tests the state of the 7th bit in X:$FFE2, sets the carry bit C
accordingly, and then complements the 7th bit in X:$FFE2.
Condition Codes:
15
14
13
LF
T
**
CCR Condition Codes:
For destination operand SR:
C — Changed if bit 0 is specified. Not affected otherwise.
V — Changed if bit 1 is specified. Not affected otherwise.
Z — Changed if bit 2 is specified. Not affected otherwise.
N — Changed if bit 3 is specified. Not affected otherwise.
U — Changed if bit 4 is specified. Not affected otherwise.
E — Changed if bit 5 is specified. Not affected otherwise.
L — Changed if bit 6 is specified. Not affected otherwise.
For other destination operands:
C — Set if bit tested is set. Cleared otherwise.
V — Not affected
Z — Not affected
N — Not affected
U — Not affected
E —Not affected
L —Not affected
MR Status Bits:
For destination operand SR:
I0 — Changed if bit 8 is specified. Not affected otherwise.
I1 — Changed if bit 9 is specified. Not affected otherwise.
S0 — Changed if bit 10 is specified. Not affected otherwise.
S1 — Changed if bit 11 is specified. Not affected otherwise.
T — Changed if bit 13 is specified. Not affected otherwise.
LF — Changed if bit 15 is specified. Not affected otherwise.
MOTOROLA
Freescale Semiconductor, Inc.
Bit Test and Change
12
11
10
9
8
S1
S0
I1
I0
**
MR
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
3
2
L
E
U
N
Z
**
CCR
BCHG
1
0
V
C
A - 33
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