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DIV
Operation:
If
D[55]
55
then
55
else
⊕
where
Assembler Syntax:
Description:
Divide the destination operand D by the source operand S and store the result in the
destination accumulator D. The 48-bit dividend must be a positive fraction which has
been sign extended to 56-bits and is stored in the full 56-bit destination accumula-
tor D. The 24-bit divisor is a signed fraction and is stored in the source operand S.
Each DIV iteration calculates one quotient bit using a nonrestoring fractional division
algorithm (see description on the next page). After the execution of the first DIV instruc-
tion, the destination operand holds both the partial remainder and the formed quotient.
The partial remainder occupies the high-order portion of the destination accumulator D
and is a signed fraction. The formed quotient occupies the low-order portion of the desti-
nation accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient
is shifted into the LS bit of the destination accumulator at the start of each DIV iteration.
The formed quotient is the true quotient if the true quotient is positive. If the true quotient
is negative, the formed quotient must be negated. Valid results are obtained only
when |D| < |S| and the operands are interpreted as fractions. Note that this condition
ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre-
cludes division by zero.
The DIV instruction calculates one quotient bit based on the divisor and the previous par-
tial remainder. To produce an N-bit quotient, the DIV instruction is executed N times
where N is the number of bits of precision desired in the quotient, 1;leN;le24. Thus, for a
full-precision (24 bit) quotient, 24 DIV iterations are required. In general, executing the
DIV instruction N times produces an N-bit quotient and a 48-bit remainder which has
(48–N) bits of precision and whose N MS bits are zeros. The partial remainder is not a
true remainder and must be corrected due to the nonrestoring nature of the division algo-
A - 58
Freescale Semiconductor, Inc.
Divide Interation
⊕
S[23]=1,
47
Destination Accumulator D
47
Destination Accumulator D
denotes the logical exclusive OR operator
DIV
S,D
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
23
0
23
0
DIV
C+S
D
C–S
D
MOTOROLA
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