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EOR
Operation:
⊕
S
D[47:24]
⊕
where
denotes the logical Exclusive OR operator
Description: Logically exclusive OR the source operand S with bits 47–24 of the desti-
nation operand D and store the result in bits 47–24 of the destination accumulator. This
instruction is a 24-bit operation. The remaining bits of the destination operand D are not
affected.
Example:
:
EOR Y1,B
:
Before Execution
Y1
B
$00:000005:000000
Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value
$000003, and the 56-bit B accumulator contains the value $00:000005:000000. The
EOR Y1,B instruction logically exclusive ORs the 24-bit value in the Y1 register with bits
47–24 of the B accumulator (B1) and stores the result in the B accumulator with bits 55–
48 and 23–0 unchanged.
Condition Codes:
15
14
13
LF
T
**
I — Set if data limiting has occurred during parallel move
N — Set if bit 47 of A or B result is set
Z— Set if bits 47 - 24 of A or B result are zero
V — Always cleared
MOTOROLA
Freescale Semiconductor, Inc.
Logical Exclusive OR
D[47:24] (parallel move)
(R2)+
;Exclusive OR Y1 with B1, update R2
$000003
12
11
10
9
8
S1
S0
I1
I0
**
MR
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Assembler Syntax:
EOR S,D (parallel move)
After Execution
Y1
$000003
$00:000006:000000
B
7
6
5
4
3
2
L
E
U
N
Z
**
CCR
EOR
1
0
V
C
A - 73
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