SOLTEK SL-61A User's Manual & Technical Reference page 35

PCI-TO-DRAM Use the default setting.
Pipeline
CPU-To-PCI Write Choose Enabled (default) or
Post Disabled.
CPU-To-PCI IDE Choose Enabled (default) or
Posting Disabled.
System BIOS Choose Enabled or Disabled
Cacheable (default). When Enabled, the access
to the system BIOS ROM addressed
at F0000H-FFFFFH is cached.
Video RAM Choose Enabled or Disabled
Cacheable (default). When Enabled, the access
to the VGA RAM addressed is
cached.
8 Bit I/O Recovery This delay happens when the CPU
Time Select Item is running so much faster than the
16 Bit I/O Recovery I/O bus that the CPU must be
Time Select Item delayed to allow for the completion
of the I/O.
The choices for 8 bit I/O are NA, 1
to 8 CPU clock. Default is 3.
The choices for 16 bit I/O are NA, 1
to 4 CPU clock. Default is 2.
Memory Hole At Choose Enabled or Disabled
15M-16M (default). In order to improve
performance, certain space in
memory can be reserved for ISA
cards. This memory must be
mapped into the memoryÕs space
below 16MB.
3. Press <ESC> and follow the screen instructions to save or
disregard your settings.
Award BIOS Setup 31