Advanced Chipset Control Submenu - Xycom CHIP4e+ User Manual

Advanced Chipset Control Submenu

Use this menu to change the values in chipset registers and optimize your system's
performance.
PhoenixBIOS Setup–Copyright 1985-95 Phoenix Technologies Ltd.
Advanced
Advanced Chipset Control
DRAM read timing:
DRAM write timing:
I/O recovery time
setting:
-PCI Features-
CPU to PCI write
buffer:
PCI to DRAM buffer:
↑↓
F1 Help
←→ Select Menu
ESC Exit
Option
DRAM read timing
DRAM write timing
I/O recovery time setting
CPU to PCI write buffer
PCI to DRAM buffer
Leave the options in this menu in their default configurations.
[Fast]
[Fast]
[0 µs]
[Enabled]
[Enabled]
Select Item -/+
Enter Select
Submenu
Description
Selects the DRAM read timing speed. Choices are "Slow," "Normal," "Fast," and "Fastest."
Selects the DRAM write timing speed. Choices are "Slow," "Normal," "Fast," and "Fastest."
Sets the minimum time required between back-to-back I/O operations. The default is 0 µs,
which allows the system to operate at the fastest rate.
Enables CPU to PCI write buffer feature for improving the CPU to PCI write performance.
Enables PCI to DRAM buffer feature for improving performance.
Note
If the line item you are
viewing has specific help,
it will be listed here.
Change Values
þ
Item Specific Help
F9 Setup Defaults
F10 Previous Values
41