Offset Registers; Offset 0 Page Register For Programming (Port Address); Offset 1 Page Register For Programming (Port Address +1) - Xycom CHIP4e+ User Manual

CHIP4e+ Manual

Offset Registers

The following registers are located starting at the I/O location defined by register
234h, bits 6 and 7.

Offset 0 Page Register for Programming (Port Address)

Offset 0 is a read-only register that checks the battery status.

Offset 1 Page Register for Programming (Port Address +1)

Offset 1 controls the SRAM paging bits.
Table 0-12. Offset 1 Page Register for Programming (Port Address +1)
Bit Signal
0 Control RAM15
1 Control RAM16
2 Control RAM17
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Reserved
20
Table 0-10. I/O Port Selection (Port Address)
I/O Port Selection
00
01
10
11
Table 0-11. Offset 0 Page Register for Programming (Port Address)
Bit Signal
0 Battery status
1-7 Reserved
Result
ROM address 15 - page control bit
ROM address 16 - page control bit
ROM address 17 - page control bit
0
0
0
0
Port Address
180h
2E0h
3E0h
300h
Result R/W
0 = Battery good R
1 = Battery failed
0 R
R/W
R/W
R/W
R/W
R
R
R/W
R
R