I/O Map - Xycom CHIP4e+ User Manual

Compact high-integration 5x86 platform with ethernet
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I/O Map

Table 0-6 depicts the CHIP4e+'s I/O map. It contains the IBM AT architecture I/O
ports, as well as some additions.
Hex Range
000-01F
020-021
022
023
025-02F
040-05F
060-06F
070-07F
080-091
092
93-9F
0A0-0BF
0C0-0DF
0F0
0F1
0F2-0F3
0F4
0F5-0F7
0F8
0F9-0FB
0FC
0FD-0FF
100
102
103-179
180-181
182-1EF
1F0-1F7
231
233
234
278-27F
280-2F7
2F8-2FF
300-36F
370-377
378-37F
380-3AF
3B0-3BB
3BC-3BF
3C0-3CF
3D0-3DF
3E0-3EF
3F0-3F7
3F8-3FF
CF8
CFC
Table 0-6. I/O Map
Device
DMA controller 1, 8237A-5 equivalent
Interrupt controller 1, 8259 equivalent
M1489/M1487 configuration index register
M1489/M1487 configuration data register
Interrupt controller 1, 8259 equivalent
Timer, 8254-2 equivalent
8742 equivalent (keyboard)
Real time clock bit 7 NMI mask
DMA page register
Reset/ Fast Gate A20
DMA page register
Interrupt controller 2, 8259 equivalent
DMA controller 2, 8237A-5 equivalent
N/A
N/A
N/A
IDE ID port
N/A
IDE Index port
N/A
IDE Data port
N/A
Available
C&T Global enable register
Available
SRAM control register (may be remapped based on I/O port 234h)
Available
IDE controller (ATdrive)
Xycom LED port
Xycom Flash control register
Xycom I/O port control register
Parallel port 2
Available
Serial port 2
Available
Alternate floppy disk controller
Parallel port 1
Available
Mono mode video
Reserved for parallel port
VGA/EGA2
CHIPS flat panel and color mode registers
Available
Primary floppy disk controller
Serial port 1
PCI configuration address register
PCI configuration data register
17

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