Siemens Solkor 7PG2113 Technical Manual page 6

7PG2113/4/5/6 Solkor Description of Operation
List of Figures
Figure 1.1-1 Functional Diagram of 7PG2113/5 Relay with Autoreclose ................................................................. 8
Figure 1.1-2 Connections Diagram for 7PG2113 Relay........................................................................................... 9
Figure 1.1-3 Connections Diagram for 7PG2115 Relay......................................................................................... 10
Figure 1.1-4 Functional Diagram of 7PG2114/6 Relay with Autoreclose ............................................................... 12
Figure 1.1-5 Connections Diagram for 7PG2114 Relay......................................................................................... 13
Figure 1.1-6 Connections Diagram for 7PG2116 Relay......................................................................................... 14
Figure 2.2-1 Relay shown withdrawn ..................................................................................................................... 16
Figure 2.2-2 Rear view of 7PG2113/4/5/6 Relay................................................................................................... 16
Figure 2.2-3 Earth Symbol ..................................................................................................................................... 16
Figure 2.3-1 Relay with standard transparent cover .............................................................................................. 17
Figure 2.5-1 Relay with Transparent cover removed ............................................................................................. 17
Figure 2.5-2 Close up of typical relay labels .......................................................................................................... 18
Figure 2.5-3 Close up of Relay Identifier................................................................................................................ 19
Figure 2.5-4 LED Indication Label.......................................................................................................................... 21
Figure 2.8-1 Binary Input Logic .............................................................................................................................. 22
Figure 2.9-1 Binary Output Logic ........................................................................................................................... 23
Figure 3.1-1 Solkor Rf schematic........................................................................................................................... 25
Figure 3.1-2 Solkor R schematic............................................................................................................................ 25
Figure 3.1-3 Solkor Rf 15kV schematic.................................................................................................................. 26
Figure 3.2-1 Through Fault, zero ohm pilots, Positive half cycle............................................................................ 28
Figure 3.2-2 Through Fault, zero ohm pilots, Negative half cycle. ......................................................................... 28
Figure 3.2-3 Through Fault, 1000 ohm pilots, Positive half cycle........................................................................... 29
Figure 3.2-4 Through Fault, 1000 ohm pilots, Negative half cycle. ........................................................................ 29
Figure 3.2-5 Through fault Rf mode, positive half cycle ......................................................................................... 30
Figure 3.2-6 Through fault Rf mode, negative half cycle........................................................................................ 30
Figure 3.2-7 Through fault Rf mode, positive half cycle ......................................................................................... 31
Figure 3.2-8 Through fault Rf mode, negative half cycle........................................................................................ 31
Figure 3.2-9 Internal fault Rf mode, positive half cycle .......................................................................................... 32
Figure 3.2-10 Internal fault Rf mode, negative half cycle ....................................................................................... 32
Figure 3.2-11 Single End Fed fault Rf mode, positive half cycle ............................................................................ 33
Figure 3.2-12 Single End Fed fault Rf mode, negative half cycle .......................................................................... 33
Figure 4.1-1 Logic Diagram: Directional Overcurrent Element (67) ....................................................................... 36
Figure 4.1-2 Logic Diagram: Instantaneous Over-current Element ........................................................................ 37
Figure 4.1-3 Logic Diagram: Time Delayed Overcurrent Element.......................................................................... 39
Figure 4.1-4 Logic Diagram: Voltage Controlled Overcurrent Protection ............................................................... 40
Figure 4.2-1 Logic Diagram: Derived Directional Earth Fault Element................................................................... 42
Figure 4.2-2 Logic Diagram: Derived Instantaneous Earth Fault Element ............................................................. 43
Figure 4.2-3 Logic Diagram: Derived Time Delayed Earth Fault Protection........................................................... 44
Figure 4.3-1 Logic Diagram: Measured Directional Earth Fault Protection ............................................................ 45
Figure 4.3-2 Logic Diagram: Measured Instantaneous Earth-fault Element........................................................... 46
Figure 4.3-3 Logic Diagram: Measured Time Delayed Earth Fault Element (51G) ................................................ 48
Figure 4.4-1 Logic Diagram: High Impedance REF (64H) ..................................................................................... 49
Figure 4.5-1 Logic Diagram: Cold Load Settings (51c) .......................................................................................... 50
Figure 4.6-1 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS)..................................................... 51
Figure 4.7-1 Logic Diagram: Relays with 4 Current Inputs Undercurrent Detector (37) ......................................... 52
Figure 4.7-2 Logic Diagram: Relays with 1 Current Inputs Undercurrent Detector (37) ......................................... 52
Figure 4.7-3 Logic Diagram: Thermal Overload Protection (49S) .......................................................................... 54
Figure 4.8-1 Logic Diagram: Under/Over Voltage Elements (27/59)...................................................................... 55
Figure 4.9-1 Logic Diagram: NPS Overvoltage Protection (47).............................................................................. 56
Figure 4.10-1 Logic Diagram: Neutral Overvoltage Element (59N)........................................................................ 57
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