Test Block Diagram With Adc32Jxx And Adc34Jxx - Texas Instruments ADC3EVM User Manual

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3.4

Test Block Diagram with ADC32Jxx and ADC34Jxx

The test set-up for evaluation of the ADC32J/34Jxx EVM with the TSW14J56 or TSW14J50 Capture Card
is shown in Figure
board clock chip LMK04828 and a sine wave for the analog input from a high-quality signal generator.
High order, narrow bandpass filters are usually required to remove phase noise and harmonic content
from the input sine waves. Since the on board clock and input sinewave are not coherent then the
resulting FFT will need to have a windowing function such as Blackman-Harris/Hamming/Hanning applied
to the data.
PC
USB
USB
Figure 18. ADC32Jxx/ADC34Jxx and TSW14J56 Test Setup Block Diagram
SLAU579D – June 2014 – Revised August 2018
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18. As seen in this figure, the evaluation setup involves a clock from a high quality on
USB Mini-B
USB Mini-B
To A, B, C, D
Channels
CHA
J1
BPF
Signal Generator
(Input Source)
Copyright © 2014–2018, Texas Instruments Incorporated
TSW14J56
J4
J20
J17
CHD
J7
LMK0
CHB CHC
4828
J3 J5
Basic Test Procedure
+5V
J11
+5V
ADC3xxxEVM and ADC3xJxxEVM
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