Evm Adc Input Circuit Configurations; Evm Dc-Coupling Configuration; Adc3Xxxx Adc Input Circuit Options; Adc34Xx Clock Input Circuit - Texas Instruments ADC3EVM User Manual

Introduction
1.4

EVM ADC Input Circuit Configurations

Figure 6 shows the ADC3xxxx ADC input circuit. The default setup has a dual 1:1 impedance ratio
transformer input circuit to achieve better phase and amplitude balance of the input signal than is typically
be produced by a single transformer input circuit.
The default input termination is 50 Ω, which is formed by two 25-Ω resistors connected to the ADC VCM
node. By default, the input circuit is set for operation within the 1st two Nyquist zones. For higher
frequency inputs, use the high-frequency input circuit shown in
1:1
Jp
Jn
0.1PF
1:1
Jp
Jn
0.1PF
Figure 7 shows the ADC3xxxx clock input circuit. The clock signal goes through 1:4 impedance ratio
transformer to increase the clock amplitude by two (that is, 1:4 impedance ratio equals to 1:2 voltage
ratio). The two 100-Ω resistors impedance transform back to the primary side as 50-Ω load impedance for
the signal source generator. For ADC evaluation, set the signal generator output to approximately
+10 dBm.
1.5

EVM DC-Coupling Configuration

The ADC3xxxx EVM family has three different hardware configurations: dual-channel serial LVDS, quad-
channel serial LVDS, and quad-channel JESD204B compliant. The following instructions are a guideline to
enable dc-coupling on the revision B EVM hardware, but can be used as a guide for other EVM revisions.
12
ADC3xxxEVM and ADC3xJxxEVM
Default ± Low Input Frequency
39nH
1:1
0.1PF
:
39nH
0.1PF
:
0.1PF
High Input Frequency
1:1
0.1PF
:
0.1PF
:
0.1PF
Figure 6. ADC3xxxx ADC Input Circuit Options
1:4
CLK IN
Figure 7. ADC34xx Clock Input Circuit
Copyright © 2014–2018, Texas Instruments Incorporated
Figure 6.
0:
:
V
CM
10pF
0.1PF
:
0.1PF
0:
10:
:
V
CM
10pF
0.1PF
:
0.1PF
10:
0.1PF
:
0.1PF
:
0.1PF
SLAU579D – June 2014 – Revised August 2018
www.ti.com
15:
:
14bit
10pF
ADC
:
15:
:
:
14bit
56nH
ADC
:
:
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