Texas Instruments ADC3EVM User Manual
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Texas Instruments ADC3EVM User Manual

Texas Instruments ADC3EVM User Manual

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This document is a user's guide for the ADC3xxxEVM and ADC3xJxxEVM. The EVMs provide a platform
for evaluating the ADC3xxx and ADC3xJxx. The ADC3xxx is a dual-channel or quad-channel, 12-bit or 14-
bit, serial LVDS interface analog-to-digital converter (ADC). The ADC3xxx comes with sampling speed
grades of 25 MSPS, 50 MSPS, 80 MSPS, and 125 MSPS. The ADC3xJxx is a dual-channel or quad-
channel, 12-bit or 14-bit, JESD204B-compliant interface ADC. The ADC3xJxx comes with sampling speed
grades of 50 MSPS, 80 MSPS, 125 MSPS, and 160 MSPS. This family of converters requires only a
single 1.8-V supply, provides flexible input clock dividers, and provides internal features for improved 1/f
(ADC32xx, ADC34xx) and SFDR performance. Throughout this document, the abbreviations EVM and
ADC3xxxx, and the term evaluation module are synonymous with the ADC3xxx EVM and ADC3xJxx EVM,
unless otherwise noted.
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SLAU579D - June 2014 - Revised August 2018
Submit Documentation Feedback
ADC3xxxEVM and ADC3xJxxEVM
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Copyright © 2014-2018, Texas Instruments Incorporated
SLAU579D - June 2014 - Revised August 2018
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User's Guide
ADC3xxxEVM and ADC3xJxxEVM
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Summary of Contents for Texas Instruments ADC3EVM

  • Page 1: Table Of Contents

    ....................... ADC32xx Tab ....................... ADC34xx Tab ......................ADC32Jxx Tab ......................ADC34Jxx Tab ............ADC32xx/ADC34xx and TSW1400 Test Setup Block Diagram SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 2 ADC32xxEVM AC-DC Coupling Resistor Swap ..............ADC3xJxxEVM AC-DC Coupling Resistor Swap Trademarks All trademarks are the property of their respective owners. ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 3: Introduction

    ADC core. For the dual, this means there are two lanes per device, and four lanes per device for the quad. See the respective device data sheet for more information on sLVDS serialization and JESD204B lane configurations. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 4: Evm Block Diagram

    FCLK 14bit CH C DCD P/M sLVDS 14bit CH D Power Supply Circuits Figure 1. Simplified ADC344x EVM Block Diagram ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 5: Simplified Adc34J4X Evm Block Diagram

    5-V, 3-A minimum power brick. All necessary voltages for the ADC EVM are derived from the 5-V input connection. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 6: Evm Power Supply

    4V to Amp TPS7A4700 Low Noise LDO 3.3V to TPS7A4700 LMK04828 Low Noise LDO TPS62080 Figure 3. Simplified EVM Power Supply ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 7 Note that the feedback resistors of the DC/DC converter must be adjusted accordingly. See the respective ADC EVM user's guide schematic for details. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 8: Evm Connectors And Jumpers

    Figure 5 show the locations of the connectors, jumpers, pushbutton switches, and LEDs. Figure 4. ADC34Jxx EVM Connector and Jumper Locations ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 9: Adc34Xx Evm Connector And Jumper Locations

    The input circuit can be configured to connect to two SMA connectors for differential signaling, if desired. Table 3 lists the connector information for the ADC3xxxx. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 10 DCLKOUT7N – LMK output test point, positive 5-V input power jack Mini USB connector for SPI GUI control CPLD JTAG port ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 11 Status LED used to indicate LMK Lock or PLL Lock Status LED for JESD SYNC D6, D7 Spare LED indicators for FMC connector 5-V power indicator SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 12: Evm Adc Input Circuit Configurations

    LVDS, and quad-channel JESD204B compliant. The following instructions are a guideline to enable dc-coupling on the revision B EVM hardware, but can be used as a guide for other EVM revisions. ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 13: Adc32Xxvm Input Coupling Configuration Resistors

    R141 DC-Coupled R135, R7, R120, R121R138, R20, R144, R3, R4, R14R18,R142, R139 R141 Figure 8. ADC32xxVM Input Coupling Configuration Resistors SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 14: Adc3Xjxx Input Coupling Configuration Resistors

    R232,R235 DC-Coupled R137, R216, R225, R227R228, R218, R217, R258, R226R219, R233, R234 R232,R235 Figure 9. ADC3xJxx Input Coupling Configuration Resistors ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 15: Software Control

    Common tab. Other specific device registers are in specific device tabs for the ADC3xxxx family and the LMK04828 for the JESD204B devices. For a more detailed description of each register, see the respective device data sheet. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 16: Common Tab

    Clk Diver – Internal clock divider to allow harmonic clocking, a higher frequency clock can be provided to the ADC and then divided down to the desired sample rate. Figure 10. Common Tab ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 17: Adc32Xx Tab

    OVR on LSB – over range indication on LSB, by default it is normal LSB function • LVDS Swing – control the LVDS swing on the LVDS signals Figure 11. ADC32xx Tab SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 18 OVR on LSB – over range indication on LSB, by default it is normal LSB function • LVDS Swing – control the LVDS swing on the LVDS signals ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 19: Adc34Xx Tab

    Software Control www.ti.com Figure 12. ADC34xx Tab SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 20 LMF Count INIT – LMF count INIT • Release ILA SEQ – delay generation of ILA sequence by 0, 1, 2, 3 MF after CGS ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 21: Adc32Jxx Tab

    Software Control www.ti.com Figure 13. ADC32Jxx Tab SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 22 LMF Count INIT – LMF count INIT • Release ILA SEQ – delay generation of ILA sequence by 0, 1, 2, 3 MF after CGS ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 23: Adc34Jxx Tab

    NOTE: Reset the board after every power cycle and then click the reconnect FTDI button on the GUI. • File→Exit: Stops the program SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 24: Basic Test Procedure

    Channels Synchronized Sources Signal Signal Generator Generator (Input Source) (CLK Source) Figure 15. ADC32xx/ADC34xx and TSW1400 Test Setup Block Diagram ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 25: Test Set-Up Connection

    4. Select number of sample points (and resulting number of FFT bins) to be used. The example shown in Figure 17 has 65536 samples. SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 26 If the basic capture at this point is correct, then the front panel options of the SPI GUI and the front panel options of the TSW1400 GUI may be varied as desired to test out different device options. ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 27: Test Block Diagram With Adc32Jxx And Adc34Jxx

    To A, B, C, D Channels LMK0 4828 Signal Generator (Input Source) Figure 18. ADC32Jxx/ADC34Jxx and TSW14J56 Test Setup Block Diagram SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 28: Test Set-Up Connection (Onboard Lmk04828 Clock)

    • JP12 – 1,2 – default condition select LDO power • JP13 – 1,2 – default condition select LDO power ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...

  • Page 29: Adc32J/34Jxx And Tsw14J56 Setup Guide

    9. Press the Capture button on the HSDC Pro GUI. 10. Observe an FFT result similar to that shown in Figure SLAU579D – June 2014 – Revised August 2018 ADC3xxxEVM and ADC3xJxxEVM Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 30 High Speed Data Converter Pro GUI may be varied as desired to test out different device SPI options. ADC3xxxEVM and ADC3xJxxEVM SLAU579D – June 2014 – Revised August 2018 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 31 • Deleted entire paragraph preceding ADC3xxxx EVM Jumper Options table ............... • Deleted several rows from ADC3xxxx EVM Jumper Options table SLAU579D – June 2014 – Revised August 2018 Revision History Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated...
  • Page 32 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
  • Page 33 FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
  • Page 34 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 2. 実験局の免許を取得後ご使用いただく。 3. 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/ /www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 3.4 European Union 3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a low-voltage power-supply network that supplies buildings used for domestic purposes.
  • Page 35 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated...
  • Page 36 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products;...

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