Table 6. Dsp Pins Tri-Stated By U11 In Pld Mode 0; Table 7. Dsp Pins Tri-Stated By U11 In Pld Mode 1; Table 8. Clocking Descriptions - Cirrus Logic CS492 Series Manual

As mentioned above, many of the PLD's I/O pins
are tri-stated. The complete list of tri-stated pins
for full external mode (PLD Mode 0) can be found
in Table 6. The complete list of tri-stated pins for
external control mode (PLD Mode 1) can be found
in Table 7.
By design, the clocking signals present at the
MCLK, LRCLK, and SCLK pins of the
CS492x/CS493xx are used to drive both the audio
input and output circuitry for the rest of the
CDB4923/300 as shown in Figure 3. This means
that the S/PDIF input, S/PDIF output, analog out-
put and analog input continue to function in the
EXTERNAL modes. The user should only drive
audio clocks in PLD Mode 0. PLD Mode 1 derives
audio clocks from the CS8414.
The three clocking configurations that the user
should be aware of when using PLD Mode 0 are:
• DSP is slave to all audio clocks - user drives
MCLK/SCLK/LRCLK
• DSP masters LRCLK/SCLK - user drives
MCLK
• DSP masters MCLK/LRCLK/SCLK - user
drives no audio clocks
Pin Name Pin
Number
MCLK 44
CMPCLK 28
CMPREQ 29
CMPDAT 27
SCLKN1 25
SLRCLKN1 26
SDATAN1 22
RESET 36
RD 5
WR 4
EXTMEM 21

Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0

DS262DB2
Pin Name Pin
Number
DATA0 17
DATA1 16
DATA2 15
DATA3 14
DATA4 11
DATA5 10
DATA6 9
DATA7 8
A1, CDIN 6
A0, SCCLK 7
SCPDIO 19
CS 18
CDB4923 CDB49300
Pin Name Pin
Number
RESET 36
RD 5
WR 4
A1, CDIN 6
A0, SCCLK 7
SCPDIO 19
CS 18

Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1

MCLK
Source
J12 The user must provide an oversampling clock on
the 23MCLK pin of stake header J12. (NOTE:
This clock signal must be +3.3 V logic when
using CS493xx)
CS8414 The CS8414 (U13) derives the sampling fre-
quency (Fs) from an incoming S/PDIF stream
and masters a 256 Fs MCLK
DSP The DSP (U1) masters MCLK, generally when
using broadcast application code

Table 8. Clocking Descriptions

Only when the correct clocking is present on the
23MCLK, 23LRCLK, and 23SCLK pins (J12),
processed audio can be heard on the analog outputs
(J13 - J20) and the digital outputs (J45 - J47). The
analog outputs J13-J20 can be found in Figure 12,
and the digital outputs can be found in Figure 13.
The information in Table 9 summarizes the opera-
tion of switch S3. The table shows the data routing
configuration, the MCLK source, and the method
of board control. This is intended as a quick refer-
ence and can also be found in Appendix J: Switch
Summary.
Pin Name Pin
Number
DATA0 17
DATA1 16
DATA2 15
DATA3 14
DATA4 11
DATA5 10
DATA6 9
DATA7 8
Description
13