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Evaluation Board for CS4923/CS49300 Families
Features
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CDB4923 demonstrates 5.1 channel decode
capability of the CS4923 family
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CDB49300 demonstrates 5.1 channel
decode capability of CS49300 family
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6 discrete analog outputs driven by CS4340
DACs
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4 S/PDIF optical outputs
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Accepts analog input, S/PDIF digital input,
Bursty compressed data
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Discrete PLL which can provide multiple
sampling frequencies
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Interfaces to a personal computer through
the parallel port
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Stake headers provide convenient location
for direct wiring to control signals from off-
board microcontroller
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Interface for external memory card
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Digital and analog patch areas
I
Digital Input
Control
Interface
DIGITAL SOUND
™
®
C R Y S T A L
P R O C E S S I N G
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Digital Output
CS8404A
CS8404A
RESET
PLD
OSC
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Description
The CDB4923 and CDB49300 customer development
boards provide the means to fully evaluate the
CS4923/4/5/6/7/8 and CS49300 family of audio decod-
ers. Compressed data can be delivered in IEC61937
format via the S/PDIF port and in bursty mode via the PC
interface. PCM data can be accepted through the digital
input connectors or from the on-board ADC. Six chan-
nels of audio are provided on the six analog outputs and
on three optical S/PDIF transmitters. CLKIN for the DSP
can be derived either from the on-board oscillator or the
external PLL. MCLK can be extracted from incoming
S/PDIF streams, generated with the external PLL, or
mastered by the audio decoder.
The CDB4923/300 incorporates a Crystal Multichannel
Audio Decoder, the CS4340 24-Bit Audio D/A Converter,
the CS8414 Digital Audio Interface Receiver, the
CS8404A Digital Audio Interface Transmitter, and the
CS5334 20-Bit Stereo A/D Converter.
ORDERING INFORMATION
CDB4923
CDB49300
CS8404A
+2.5V
+3.3V
CS492x
CS493xx
Patch Area
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
CDB4923
CDB49300
Evaluation Board
Evaluation Board
CS4340
Analog
CS4340
Output
CS4340
Stereo
CS5334
Analog In
JAN '00
DS262DB2
1
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Table of Contents
Related Manuals for Cirrus Logic CS492 Series
Summary of Contents for Cirrus Logic CS492 Series
- Page 1 P R O C E S S I N G Patch Area This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. JAN ‘00 Copyright Cirrus Logic, Inc. 2000 P.O. Box 17847, Austin, Texas 78760...
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Page 2: Table Of Contents
(electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture... - Page 3 CDB4923 CDB49300 12. APPENDIX F: BOARD CONTROL SOFTWARE ..............39 13. APPENDIX G: IC COMPONENT LISTING BY FUNCTION ..........42 13.1 Power ..........................42 13.2 Reset ..........................42 13.3 Clocking.......................... 42 13.4 Signal Routing/Level Conversion ................... 42 13.5 DSP ..........................42 13.6 Input..........................
- Page 4 CDB4923 CDB49300 LIST OF TABLES Table 1. CS492x/CS493xx Host Interface Mode Selection............. 8 Table 2. Data Selection Modes (PLD version AB-X)..............10 Table 3. PROVIDED Data Selection Modes (PLD version AB-X) ..........11 Table 4. Digital Audio Sources ...................... 11 Table 5.
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Page 5: Cdb4923 Vs. Cdb49300
CDB4923 CDB49300 C155 = 0.22 µF 1. CDB4923 VS. CDB49300 • The CDB4923 and CDB49300 are two customer The relevant PLL filter components for the development boards built from a single platform - CDB49300 are: the CDB4923/300. This development board replac- •... -
Page 6: Power Requirements
CDB4923 CDB49300 proper voltage), configure the audio decoder for for the DSP processor clock, it can also be used to different host communication modes and select the master the system oversampling clock, MCLK. clock source for the DSP (internal PLL or external The CDB4923/300 features six channels of analog clock). -
Page 7: Dolby Considerations
CDB4923 CDB49300 age regulators on the board (U8 and U27) which This document and all other documentation per- are used to power the DSP and the I/O pads of the taining to the CS493xx family of decoders can be PLD (U11). The +12 V and -12 V supplies are used found at the following website: to power the input buffers on the analog side of the http://www.cirrus.com/products/overviews/cs49300.html... -
Page 8: External Memory
CDB4923 CDB49300 PSEL==1 when configuring for I C mode because CRD4923-MEM external memory board is tailored PSEL and SCDIO are multiplexed onto the same for the CDB4923. The schematic for CRD4923- pin. MEM can be found in Figure 20. Two of the DSP jumpers are designed to act as cur- The CS493xx family has integrated DTS tables, so rent measurement points for the CS492x/CS493xx. -
Page 9: Data Selection
CDB4923 CDB49300 Digital Input Digital Output CS4340 CS8404A CS8404A CS8404A +2.5V Analog +3.3V CS4340 Output RESET CRD4923-MEM CDB49300-MEM CS4340 CS492x CS493xx Control Interface Stereo CS5334 Analog In Patch Area Figure 1. External Memory Example input ports of the DSP. These configuration allows DIP switch S3. -
Page 10: Provided Mode
CDB4923 CDB49300 The two major PLD modes for the CDB4923/300 Provided Mode are the PROVIDED resource mode and the EX- When the user has chosen a PROVIDED resource TERNAL interface mode. When a PROVIDED mode, the PLD Mode determines the source of au- mode is chosen all clocks are provided by the dem- dio data for the two data pins of the DSP (CMP- onstration board, all audio data passes through the... -
Page 11: Figure 2. Cdb4923/300 Data Paths
CDB4923 CDB49300 CS4340 CS8404A CS8404A CS8404A CS4340 CS8414 XMT958 Data CS4340 PCM Out CS492x CS493x Parallel Compressed Data Stereo PCM CS5334 Figure 2. CDB4923/300 Data Paths DATA_SEL2 DATA_SEL1 DATA_SEL0 CS492x/CS493xx CS492x/CS493xx MCLK Mode CMPDAT SDATAN1 SOURCE A/D — CS5334 S/PDIF — CS8414 S/PDIF —... -
Page 12: Audio Clocking
CDB4923 CDB49300 5.1.3 Audio Clocking External Mode The EXTERNAL mode is designed to allow users The audio clocking scheme is illustrated below in to drive the DSP directly with an external micro- Figure 3. Note that MCLK is bidirectional with re- controller. -
Page 13: Table 6. Dsp Pins Tri-Stated By U11 In Pld Mode 0
CDB4923 CDB49300 As mentioned above, many of the PLD’s I/O pins Pin Name Pin Name are tri-stated. The complete list of tri-stated pins Number Number for full external mode (PLD Mode 0) can be found DATA0 RESET in Table 6. The complete list of tri-stated pins for DATA1 external control mode (PLD Mode 1) can be found DATA2... -
Page 14: Clocking
CDB4923 CDB49300 6. CLOCKING Since the PLL (U26) and the OSCILLATOR (Y1) are co-dependent, only one can be used at any giv- There are four major clocks routed across the en time. Jumper J37 is used to select the source of CDB4923/300: CLKIN for the DSP, MCLK, LR- the main DSP clock. -
Page 15: Mclk
CDB4923 CDB49300 ally, both jumpers of J37 should be set to the OSC modes can select between an MCLK which is sim- position. In this clocking configuration you should ply the frequency of the on-board oscillator (Y1), not use any modes which list OSC/PLL as the or a programmable MCLK generated by the exter- MCLK source while Y1 is 27 MHz. -
Page 16: Input
CDB4923 CDB49300 7. INPUT PARLLPLY.EXE program found on the included floppy. Audio delivered across the S/PDIF inter- Analog Input face comes from a digital source such as a DVD A stereo input is provided at RCA jacks J55 and player. J56. -
Page 17: Output
CDB4923 CDB49300 8. OUTPUT down, and during audio clock discontinuities if the reset period is violated. Analog Output Digital Output The six discrete outputs provided on the CDB4923/300 are driven by CS4340 D/A convert- The signals present on analog outputs J13-J16, J18, ers. -
Page 18: Appendix A: Schematics
CDB4923 CDB49300 9. APPENDIX A: SCHEMATICS DS262DB2... -
Page 19: Figure 5. System Power
CDB4923 CDB49300 DS262DB2... -
Page 20: Figure 6. Pc Interface
CDB4923 CDB49300 DS262DB2... -
Page 21: Figure 7. Control Logic
CDB4923 CDB49300 DS262DB2... -
Page 22: Figure 8. Clocking
CDB4923 CDB49300 DS262DB2... -
Page 23: Figure 9. Analog Input
CDB4923 CDB49300 DS262DB2... -
Page 24: Figure 10. Digital Input
CDB4923 CDB49300 DS262DB2... -
Page 25: Figure 11. D/A Converters
CDB4923 CDB49300 DS262DB2... -
Page 26: Figure 12. Analog Output
CDB4923 CDB49300 DS262DB2... -
Page 27: Figure 13. Digital Output
CDB4923 CDB49300 DS262DB2... -
Page 28: Figure 14. Top Layer
CDB4923 CDB49300 DS262DB2... -
Page 29: Figure 15. Bottom Layer
CDB4923 CDB49300 DS262DB2... -
Page 30: Figure 16. Sstop
CDB4923 CDB49300 DS262DB2... -
Page 31: Figure 17. Asystop
CDB4923 CDB49300 DS262DB2... -
Page 32: Figure 18. Layer 2
CDB4923 CDB49300 DS262DB2... -
Page 33: Figure 19. Layer 3
CDB4923 CDB49300 DS262DB2... -
Page 34: Appendix D: Bill Of Materials
10. APPENDIX D: BILL OF MATERIALS Item Quan Reference Part Number Manufacturer Description C1,C7,C8,C9,C91,C96,C101,C129,C132,C15 T491B105M035AS KEMET CAP, 1UF, TANT, 3528, 35V, 10% 9,C160,C163,C164,C167,C168 C4,C10,C11,C12,C66,C67,C68,C69,C71,C72, C1206C104K5RAC KEMET CAP, .1UF, X7R, 1206, 50V, 10% C90,C95,C100,C106,C107,C108,C109,C110, C111,C112,C130,C133,C138,C139,C141,C14 3,C149,C150,C151,C152,C153,C157,C161,C 162,C165,C166,C169,C170,C172,C174,C175, C176 C18,C24,C28,C36,C41,C48 T491B335K020AS KEMET CAP, 3.3UF, TANT, 3528, 20V, 10% C19,C20,C25,C26,C29,C30,C37,C38,C42,C4 C1206C152F5GAC... - Page 35 Item Quan Reference Part Number Manufacturer Description 111-0104-001 JOHNSON COMPONENTS BINDING POST, GREEN 747238-4 CONNECTOR, D-SUB, 25-PIN, MALE, RA TORX173 TOSHIBA OPTICAL TOSLINK RECIEVER J43,J45,J46,J47 TOTX173 TOSHIBA OPTICAL TRANSMITTER 43LS475 MILLLER INDUCTOR, 47UF Q1,Q5,Q9 MMUN2111LT1 MOTOROLA TRANSISTOR, PNP, SOT-23 Q2,Q6,Q10 MMUN2211LT1 MOTOROLA TRANSISTOR, NPN, SOT-23...
- Page 36 Item Quan Reference Part Number Manufacturer Description PT645TL50 C&K SWITCH,PB,DPST,5 LEG S1,S2,S3 76SB03 GRAYHILL DIP SWITCH, 3 POSITION 76SB04 GRAYHILL DIP SWITCH, 4 POSITION TP5,TP17,TP18,TP19,TP20,TP21,TP22,TP23 TSW-101-07-G-S SAMTEC STAKE HEADER, 1X1, .1"CENTER, GOLD ,TP24,TP25,TP26,TP27,TP28,TP29 CS493001-CL CRYSTAL 540-93-044-24-000 MILL-MAX SOCKET-D.U.T. HOLE, PLCC-44, PIH LM3940IT-3.3 NATIONAL +3.3V REGULATOR, TO-220...
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Page 37: Appendix E: External Memory Schematics
CDB4923 CDB49300 11. APPENDIX E: EXTERNAL MEMORY SCHEMATICS DS262DB2... -
Page 38: Figure 21. Cdb49300-Mem Schematic
D[7:0] uC17 uC16 EMAD[7:0] uC15 EMAD0 EMAD1 EMAD2 EMAD3 EMAD4 EMAD5 +3.3V EMAD6 uC18 EMAD7 #EXTMEM #EMWR +3.3V #EMOE #EMOE #EMOE +3.3V +3.3V 74LVC574 74LVC574 74LVC574 0.1uF 0.1uF 0.1uF AT27LV020A 0.1uF A[16:0] +3.3V +3.3V uC18 +3.3V 0.1uF 47uF #ABOOT 74LVC125 0.1uF #EXTMEM #uC18... -
Page 39: Appendix F: Board Control Software
CDB4923 CDB49300 12. APPENDIX F: BOARD CONTROL SOFTWARE There is a suite of programs used to control the chosen from the command line with the '-m' option. CDB4923/300. The definitions given refer to It should be remembered that the mode chosen ‘CDB30’... - Page 40 CDB4923 CDB49300 * = default EXAMPLES: cdb23cmd 000001 -p3bc cdb23cmd -fac3.cfg -mS -p3bc CDB30_RD - program used to read back responses from the CS492x/CS493xx. If the INTREQ pin is not low when CDB30_RD is executed, the program will wait until INTREQ drops.
- Page 41 CDB4923 CDB49300 -m = Parallel control mode Y = n (INTEL) or m (MOTOROLA)* -c = Chunk Size NNN = transfer size in words (252*) * = default CDB30_AD - program used to demonstrate autodetection on the CDB4923/300 only with IEC61937 or IEC60958 input.
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Page 42: Appendix G: Ic Component Listing By Function
CDB4923 CDB49300 13. APPENDIX G: IC COMPONENT LISTING BY FUNCTION 13.1 POWER 3.3 V Voltage Regulator {Figure 5} 2.5 V Voltage Regulator {Figure 5} 13.2 RESET MAX708 Reset chip {Figure 7} 13.3 CLOCKING MK2744 Programmable Phase Locked Loop (PLL) {Figure 8} Oscillator {Figure 8} 13.4 SIGNAL ROUTING/LEVEL CONVERSION... -
Page 43: Appendix H: Jumpers Listed By Function
CDB4923 CDB49300 14. APPENDIX H: JUMPERS LISTED BY FUNCTION 14.1 AUDIO INPUT JUMPERS This jumper is used to select the input connector which is being used to receive S/PDIF data. Placing the jumper in the ’RCA’ position enables the RCA jack, and placing the jumper in the ’OPT’... -
Page 44: Power Jumpers
CDB4923 CDB49300 header can be used to probe signals during normal operation, and may be used as a wirewrap point when using Data Selection Mode 0 or 1, as detailed in the Data Selection section of this datasheet. Stake header providing access to all serial audio data and clock pins. This header can be used to probe signals during normal operation, and may be used as a wirewrap point when using Data Selection Mode 0 or 1, as detailed in the Data Selection section of this datasheet This jumper selects the pull-up/pull-down state of the CS492x/CS493xx’s PSEL pin. - Page 45 CDB4923 CDB49300 adjusting this jumper. Y1 must be a 27 MHz oscillator before attempting to use U26. When both jumpers are in the ’PLL’ position, U26 will drive the CLKIN pin of the CS492x/CS493xx with the configured PCLK (refer to Table 12 or Table 22), and the system MCLK will be driven by ACLK.
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Page 46: Appendix I: Jumpers Listed By Number
CDB4923 CDB49300 15. APPENDIX I: JUMPERS LISTED BY NUMBER NOTE: Each jumper listed below is described in Appendix H: Jumpers Listed by Function. The relevant section heading is listed beside each jumper name in braces {}. CS492x/CS493xx DSP clock {DSP Jumpers} Default: CLKIN CS492x/CS493xx WR pin {DSP Jumpers} Default: HI... -
Page 47: Appendix J: Switch Summary
CDB4923 CDB49300 16. APPENDIX J: SWITCH SUMMARY Table 21 shows all of the digital output formats that can be selected for the CS8414 with switch S1. Table 18 lists the jumper settings required for all Please see the CS8414 datasheet for a more de- four host interface modes of the CS492x/CS493xx. -
Page 48: Table 22. Pclk Configurations
CDB4923 CDB49300 PCLK Frequency Audio Serial Port Format 33.33 MHz FSYNC & SCK Output 54 MHz Left/Right, 16-24 Bits 66.66 MHz Word Sync, 16-24 Bits 80 MHz Reserved 32 MHz Left/Right, I S (default) 81 MHz LSB Justified, 16 Bits 50 MHz LSB Justified, 18 Bits 40 MHz... - Page 49 • Notes •...
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