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Cirrus Logic CDB61584A Manual

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FEATURES
Socketed CS61584A Dual Line Interface
All Required Components for CS61584A
Evaluation
Locations to Evaluate Protection Circuitry
LED Status Indications for Alarm Conditions
Support for Hardware and Host Modes
ORDERING INFORMATION:
CDB61584A
CHANNEL 1
CHANNEL 2
DS261DB2
5V+ 0V
TCLK1
TPOS1
(TDATA1)
TNEG1
RCLK1
RPOS1
(RDATA1)
RNEG1
(BPV1)
RESET
V+
CIRCUIT
CS61584A
Hardware Control
and Mode Circuit
LED Status
Indicators
Serial Interface
Control Circuit
TCLK2
TPOS2
(TDATA2)
TNEG2
RCLK2
RPOS2
(RDATA2)
RNEG2
(BPV2)
Copyright © Cirrus Logic, Inc. 1998
(All Rights Reserved)
Dual Line
Interface Unit
DESCRIPTION
The evaluation board includes a socketed CS61584A
dual line interface device and all support components
necessary for evaluation. The board is powered by an
external +5 Volt supply.
The board may be configured for 100Ω twisted-pair T1,
75Ω coax E1, or 120Ω twisted-pair E1 operation. Bind-
ing posts and bantam jacks are provided for line
interface connections. Several BNC connectors provide
clock and data I/O at the system interface. Reference
timing may be derived from a quartz crystal, crystal os-
cillator, or an external reference clock. Four LED
indicators monitor device alarm conditions.
TTIP1
TRING1
RTIP1
RRING1
REFCLK
Oscillator
XTL
Circuit
TTIP2
TRING2
RTIP2
RRING2
CDB61584A
Product Databook
CHANNEL 1
CHANNEL 2
MAR '98

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Summary of Contents for Cirrus Logic CDB61584A

  • Page 1 Mode Circuit Oscillator LED Status Circuit Indicators Serial Interface Control Circuit TTIP2 TCLK2 TPOS2 (TDATA2) TRING2 TNEG2 CHANNEL 2 RTIP2 CHANNEL 2 RCLK2 RPOS2 (RDATA2) RNEG2 RRING2 (BPV2) Copyright © Cirrus Logic, Inc. 1998 DS261DB2 MAR ‘98 (All Rights Reserved)
  • Page 2: Power Supply

    Hardware mode. The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a loss The CDB61584A switches and functions are listed of signal. If coder mode is enabled in the below: CS61584A register set, the AIS alarm condition is...
  • Page 3: Transmit Circuit

    CDB61584A Dual Line Interface Unit provided when headers J7 and J13 are jumpered in pacitor is required for 100Ω twisted-pair T1 or the "AIS" position. The AIS1 and AIS2 LED indi- 120Ω twisted-pair E1 applications. A 470 pF ca- cators illuminate when the line interface receiver pacitor is required for 75Ω...
  • Page 4 CDB61584A Dual Line Interface Unit REFERENCE CLOCK JTAG ACCESS The CDB61584A requires a T1 or E1 reference The CS61584A implements JTAG boundary scan clock for operation. This clock may operate at ei- to support board-level testing. Interface port J56 ther a 1-X rate (1.544 MHz or 2.048 MHz) or an 8- provides access to the four JTAG pins on the X rate (12.352 MHz or 16.384 MHz) and can be...
  • Page 5 2) A jumper must not be placed on header J10 operation or the CLKE bit in the Control A reg- when using the CDB61584A. ister must be set to a 1 during Host mode oper- 3) Component locations R3-R4, R14-R15, C1, ation.
  • Page 6 CDB61584A Dual Line Interface Unit RCLK1 51.1 100pF .1 µ F RPOS1 (RDATA1) 51.1 100pF RNEG1 (BPV1) 51.1 100pF TCLK1 CS61584A 100pF CHANNEL 1 TPOS RCLK1 (TDATA1) RPOS1 RNEG1 100pF 51.1 TCLK1 51.1 TNEG TPOS1 TNEG1 100pF 51.1 LOS1 J-TDO...
  • Page 7 CDB61584A Dual Line Interface Unit RCLK2 51.1 100pF RPOS2 (RDATA2) 51.1 100pF .1 µ F RNEG2 (BPV2) 51.1 100pF TCLK2 100pF CS61584A N/C-3 60 CHANNEL 2 TPOS2 RCLK2 (TDATA2) RPOS2 100pF RNEG2 51.1 TCLK2 51.1 TNEG2 TPOS2 TNEG2 100pF 51.1...
  • Page 8 CDB61584A Dual Line Interface Unit 51.1 100 pF 51.1 100 pF J-TD0 3.92k J-TD1 J-TMS T-TCK CON01 24 TAOS2 CON11 23 TAOS1 CON21 22 LLOOP CON31 21 RLOOP2 20 RLOOP1 19 PD1 18 PD2 CON02 17 ATTEN0 CON12 ATTEN0 16 ATTEN1...
  • Page 9 CDB61584A Dual Line Interface Unit CS61584A TIMING CIRCUITRY .1µF .1µF .1µF 1.0 µ F J 10 (must not be jumped) REFCLK .1µF Figure 4. Timing Circuitry DS261DB2...
  • Page 10 CDB61584A Dual Line Interface Unit 47 µ F Prototyping Area Figure 5. Common Circuitry DS261DB2...
  • Page 11 • Notes •...
  • Page 12 (electronic, mechanical, photographic, or otherwise). Fur- thermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc.