Hardware mode. The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a loss The CDB61584A switches and functions are listed of signal. If coder mode is enabled in the below: CS61584A register set, the AIS alarm condition is...
CDB61584A Dual Line Interface Unit provided when headers J7 and J13 are jumpered in pacitor is required for 100Ω twisted-pair T1 or the "AIS" position. The AIS1 and AIS2 LED indi- 120Ω twisted-pair E1 applications. A 470 pF ca- cators illuminate when the line interface receiver pacitor is required for 75Ω...
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CDB61584A Dual Line Interface Unit REFERENCE CLOCK JTAG ACCESS The CDB61584A requires a T1 or E1 reference The CS61584A implements JTAG boundary scan clock for operation. This clock may operate at ei- to support board-level testing. Interface port J56 ther a 1-X rate (1.544 MHz or 2.048 MHz) or an 8- provides access to the four JTAG pins on the X rate (12.352 MHz or 16.384 MHz) and can be...
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2) A jumper must not be placed on header J10 operation or the CLKE bit in the Control A reg- when using the CDB61584A. ister must be set to a 1 during Host mode oper- 3) Component locations R3-R4, R14-R15, C1, ation.
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(electronic, mechanical, photographic, or otherwise). Fur- thermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc.
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