Table of Contents
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Features
Line-level Analog Inputs
–
4 RCA Input Jacks
Line-Level & HP Analog Output
–
Stereo Headphone Out Jack
–
RCA Audio Jacks for Headphone and Line
Outputs
S/PDIF Interface
–
CS8416 Digital Audio Receiver
–
CS8406 Digital Audio Transmitter
I/O Stake Headers and SMA Connectors
™
–
External I²C
–
External DSP Serial Audio I/O Accessibility
–
Direct DSP Serial Audio I/O accessibility
with CS42L55 through SMA connectors
Multiple Power Supply options via USB, Battery
or External Power Supplies
1.65 V to 3.3 V Logic Interface
FlexGUI S/W Control - Windows
–
Pre-defined & User-configurable Scripts
PC Control
Serial
USB
S/PDIF Rx
S/PDIF Tx
I/O Stake Headers for Audio
Precision's Programmable Serial
Interface Adapter (PSIA)
http://www.cirrus.com
Evaluation Board for CS42L55
Control Port Accessibility
®
Compatible
Board Power
External 5.0 V
Supply
LDO
I²C for all
applicable
24 MHz
devices
Oscillator
PLL
FPGA
Clock/Data Routing
Clock dividers and PLL used
to derive all applicable Fs
from 24 MHz oscillator
SRC (Tx)
SRC (Rx)
Copyright © Cirrus Logic, Inc. 2008
Description
The CDB42L55 is the ideal evaluation platform solution to test
and evaluate the CS42L55.The CS42L55 is a highly integrat-
ed, 24-bit, ultra-low-power stereo CODEC based on multi-bit
Delta-Sigma modulation suitable for low-power portable sys-
tem applications. Use of the board requires an analog or digi-
tal signal source, an analyzer, and power supplies. A
Windows PC-compatible computer is also needed in order to
configure the CS42L55 and the board.
System timing can be provided by the CS8416 S/PDIF Re-
ceiver, by the CS42L55 supplied with a master clock, or via an
I/O stake header with a DSP connected.
RCA connectors are provided for CS42L55 analog inputs and
HP/Line outputs. A 1/8 inch audio jack is provided for head-
phone stereo out. Digital I/O connections are available via
RCA phono or optical connectors to the CS8416 and CS8406
(S/PDIF Rx and Tx).
The CDB42L55 is programmed via the PC's USB using Cirrus
Logic's Microsoft
evaluation board may also be configured to accept external
timing and data signals for operation in a user application dur-
ing system development.
Ordering Information
CDB42L55
CODEC Power
LDO's
1.8 V
VL, VCP, VLDO, VA
2.5 V
MUX
3.3 V
3.3 V (VL only)
Circuit Break for
External System
Interface
PCM
Clocks/Data
I²C Clocks/
Data
Tri-state
Buffers
Stereo HP
HP
Jack
I/O SMA Connectors
for External System
Interface
(All Rights Reserved)
CDB42L55
®
®
Windows
-based FlexGUI software. The
1.8 V
x3
Buck
AAA Alkaline
(not included)
Stereo
Input 1
CS42L55
Stereo
Input 2
Stereo Line
Output
Output
Evaluation Board
DEC '08
DS773DB1
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Related Manuals for Cirrus Logic CDB42L55
Summary of Contents for Cirrus Logic CDB42L55
- Page 1 CDB42L55 Evaluation Board for CS42L55 Features Description The CDB42L55 is the ideal evaluation platform solution to test Line-level Analog Inputs and evaluate the CS42L55.The CS42L55 is a highly integrat- – 4 RCA Input Jacks ed, 24-bit, ultra-low-power stereo CODEC based on multi-bit Delta-Sigma modulation suitable for low-power portable sys- Line-Level &...
-
Page 2: Table Of Contents
4.5 Analog Output Volume Tab ......................15 4.6 Register Maps Tab ......................... 16 5. SYSTEM CONNECTIONS AND JUMPERS ..................17 6. PERFORMANCE PLOTS ........................19 7. CDB42L55 BLOCK DIAGRAM ......................24 8. CDB42L55 SCHEMATICS ........................25 9. CDB42L55 LAYOUT ..........................30 10. REVISION HISTORY .......................... 35... - Page 3 CDB42L55 LIST OF FIGURES Figure 1.Quick Start Board Layout ......................4 Figure 2.S/PDIF or PSIA In to Analog Out ....................8 Figure 3.Analog In to S/PDIF or PSIA Out ....................9 Figure 4.Board Configuration Tab ......................11 Figure 5.CODEC Configuration Tab ......................12 Figure 6.ADC Input Channel Volume Tab ....................
-
Page 4: Quick Start Guide
CDB42L55 1 QUICK START GUIDE The following figure is a simplified quick-start guide made for user convenience. The guide configures the board with a 1.8 V power supply to VLDO, VA and VCP and a 3.3 V power supply to VL. The user may choose from steps 7 through 10 depending on the desired measurement. -
Page 5: System Overview
USB. NOTE: The minimum current required for board operation is approximately 300 mA. It may therefore be necessary to connect the CDB42L55 directly to the USB port on the PC as opposed to a hub or keyboard port where the current might be limited. -
Page 6: Cs8421 Sample Rate Converter (Tx Src To Cs42L55)
CDB42L55 Configuration of the CS8416 is made using controls in the “Board Configuration” tab of the Cirrus FlexGUI software. Section 3 “Configuration Options” on page 8 Section 4 “Software Mode Control” on page 10 provide configuration examples and software details. -
Page 7: Oscillator
CDB42L55 Oscillator The socketed on-board oscillator can be selected as the system master clock source by using the selections on the “Board Configuration” tab of the Cirrus FlexGUI. ‘Software Mode Control” on page 10 provides con- figuration details. The oscillator is mounted in pin sockets, allowing easy removal or replacement. The device footprint on the board will accommodate full- or half-can-sized oscillators. -
Page 8: Configuration Options
CDB42L55 3 CONFIGURATION OPTIONS This section highlights two common configurations for the CDB42L55. It provides a basic understanding of how the various components on the board work together. S/PDIF or PSIA In to Analog Out The CS42L55 analog back-end performance can be tested by selecting the “SPDIF In to Analog Out -- Analog In to S/PDIF Out”... -
Page 9: Analog In To S/Pdif Or Psia Out
CDB42L55 Analog In to S/PDIF or PSIA Out The CS42L55 analog front-end performance can be tested by selecting the “SPDIF In to Analog Out -- Analog In to S/PDIF Out” or “PSIA In to Analog Out -- Analog In to PSIA Out” quick setup file provided with the software package. -
Page 10: Software Mode Control
6. Set up the CS42L55 in the “CODEC...” tabs as desired. 7. Begin evaluating the CS42L55. For quick set-up, the CDB42L55 may, alternatively, be configured by loading a predefined sample script file: 8. On the File menu, click "Restore Board Registers..."... -
Page 11: Board Configuration Tab
CDB42L55 Board Configuration Tab The “Board Configuration” tab provides high-level control of signal routing on the CDB42L55. The controls in this tab are used to setup the CS8416, CS8406, TxSRC, RxSRC and the FPGA Routing and are divided into separate sections or control groups for each of these individual components. A description of each con- trol group is outlined below. -
Page 12: Codec Configuration Tab
CDB42L55 CODEC Configuration Tab The “CODEC Configuration” tab provides high-level control of the CS42L55 register settings. Status text de- tailing the CODEC’s specific configuration appears directly below the associated control. This text will change depending on the setting of the associated control. A description of each control group is outlined below. -
Page 13: Analog Input Volume Tab
CDB42L55 Analog Input Volume Tab The “Analog Input Volume” tab provides high-level control of all volume settings in the ADC of the CS42L55. Status text detailing the CODEC’s specific configuration is shown inside the control group of the affected control. This text will change depending on the setting of the associated control. A description of each con- trol group is outlined below (a description of each register is included in the CS42L55 data sheet): Digital Volume Control - Digital volume controls and adjustments (ADC output). -
Page 14: Dsp Engine Tab
CDB42L55 DSP Engine Tab The “DSP Engine” tab provides high-level control functions to modify the SDIN (PCM) data volume level, the ADC output/SDIN mix volume level, Tone Control and Beep Generator. Status text detailing the CO- DEC’s specific configuration is shown inside the control group of the affected control. This text will change depending on the setting of the associated control. -
Page 15: Analog Output Volume Tab
CDB42L55 Analog Output Volume Tab The “Analog Output Volume” tab provides high-level control of the CS42L55 Class H output amplifier, HP/Line output volume levels, charge pump frequency and overall master volume level. This tab also pro- vides control functions for the DAC channel limiter. Status text detailing the CODEC’s specific configuration is shown in read-only edit boxes. -
Page 16: Register Maps Tab
CDB42L55 Register Maps Tab The Register Maps tabs provide low-level control of the CS42L55, CS8416, CS8406, CS8421, FPGA and GPIO register settings. Register values can be modified bit-wise or byte-wise. “Left-clicking” on a particular register accesses that register and shows its contents at the bottom. The user can change the register con- tents by using the push-buttons, by selecting a particular bit and typing in the new bit value or by selecting the register in the map and typing in a new hex value. -
Page 17: System Connections And Jumpers
CDB42L55 5 SYSTEM CONNECTIONS AND JUMPERS CONNECTOR INPUT/OUTPUT SIGNAL PRESENT EXT. +5V Input +5V power supply TP10 Input GND reference Ext. Input Input +4.5V external power supply for U4 buck regulator Input GND reference Input Socket for +1.5 V AAA batteries... -
Page 18: Table 2. Jumper Settings
CDB42L55 LABEL PURPOSE POSITION FUNCTION SELECTED *+1.8V Voltage source is +1.8 V regulator. +2.5V Voltage source is +2.5 V regulator. Selects source of voltage for the VL supply +3.3V Voltage source is +3.3 V regulator. +1.8VB Voltage source is +1.8V from battery. -
Page 19: Performance Plots
CDB42L55 6 PERFORMANCE PLOTS Test conditions (unless otherwise specified): T = 25°C; VA=VCP=VLDO=VL=1.8 V; input test signal is a full-scale 997 Hz sine wave; dB values relative to full-scale output; measurement bandwidth 20 Hz to 20 kHz (un-weighted); sample frequency = 48 kHz; +2 dB analog gain for Line Output path; -4 dB analog gain for Headphone Output path;... -
Page 20: Figure 14.Fft - Analog In To Digital Out - No Input
CDB42L55 -100 -100 -120 -120 -140 -140 Figure 14. Figure 15. FFT - Analog In to Digital Out - no input FFT Crosstalk - Analog In to Digital Out @ -1 dBFS -0.5 -1.5 -2.5 -125 -100 Figure 16. Freq. Response - Analog In to Digital Out Figure 17. -
Page 21: Figure 20.Thd+N Vs Volume - Digital In To Hp Out
CDB42L55 Master Volume (Digital) -100 -100 Headphone Volume -105 (Analog) -120 -110 -115 -140 -120 dBr A Figure 20. THD+N vs. Volume - Digital In to HP Out Figure 21. FFT - Digital In to HP Out @ 0 dBFS... -
Page 22: Figure 26.Fft Crosstalk - Digital In To Hp Out @ 0 Dbfs
CDB42L55 -100 -120 -140 -100 Figure 26. FFT Crosstalk - Digital In to HP Out @ 0 dBFS Figure 27. THD+N vs. Freq. - Digital In to Line Out Master Volume (Digital) -100 Line Volume -110 (Analog) -100 -100 -120... -
Page 23: Figure 32.Fft - Digital In To Line Out - No Input
CDB42L55 -100 -100 -120 -120 -140 -140 Figure 32. Figure 33. FFT - Digital In to Line Out - no input FFT Crosstalk - Digital In to Line Out @ 0 dBFS -125 -100 dBFS Figure 34. Figure 35. Freq. Response - Digital In to Line Out... -
Page 24: Cdb42L55 Block Diagram
7 CDB42L55 BLOCK DIAGRAM CODEC Power PC Control Board Power External 5.0 V LDO’s Supply 1.8 V Serial 1.8 V VL, VCP, VLDO, VA Buck 2.5 V AAA Alkaline 3.3 V 3.3 V (VL only) (not included) I²C for all... -
Page 25: Cdb42L55 Schematics
8 CDB42L55 SCHEMATICS Figure 37. CS42L55 & Analog I/O (Schematic Sheet 1) -
Page 26: Figure 38.S/Pdif & Digital Interface (Schematic Sheet 2)
Figure 38. S/PDIF & Digital Interface (Schematic Sheet 2) -
Page 27: Figure 39.Pll, Oscillator And External I/O Connections (Schematic Sheet 3)
Figure 39. PLL, oscillator and external I/O connections (Schematic Sheet 3) -
Page 28: Figure 40.Microcontroller And Fpga (Schematic Sheet 4)
Figure 40. Microcontroller and FPGA (Schematic Sheet 4) -
Page 29: Figure 41.Power (Schematic Sheet 5)
Figure 41. Power (Schematic Sheet 5) -
Page 30: Cdb42L55 Layout
9 CDB42L55 LAYOUT Figure 42. Silk Screen... -
Page 31: Figure 43.Top-Side Layer
Figure 43. Top-Side Layer... -
Page 32: Figure 44.Gnd (Layer 2)
Figure 44. GND (Layer 2) -
Page 33: Figure 45.Power (Layer 3)
Figure 45. Power (Layer 3) -
Page 34: Figure 46.Bottom Side Layer
Figure 46. Bottom Side Layer... -
Page 35: Revision History
CDB42L55 10 REVISION HISTORY Revision Changes Initial Release DS773DB1... - Page 36 TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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