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Octal E1 Line Interface Evaluation Board
Features
Socketed CS61880 Octal Line Interface Unit
Binding post connectors for power and line
interface connections
Components supplied for all operational
modes E1 75 Ω and E1 120 Ω
Socketed termination circuitry for easy
testing
Connector for IEEE 1149.1 JTAG Boundary
Scan
LED Indicators for Loss of Signal (LOS) and
power
Supports Hardware, Serial, and Parallel Host
Modes
Easy-to-use evaluation software
On-board socketed reference clock oscillator
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Description
The CS61880 evaluation board is used to demonstrate
the functions of a CS61880 Octal Line Interface Unit in
either E1 75 Ω or E1 120 Ω.
The evaluation board can be operated in either Hard-
ware mode or Host mode. In Hardware mode, switches
and bed stake headers are used to control the line con-
figuration and channel operations for all eight channels.
In Host mode (Serial or Parallel), the evaluation soft-
ware, switches, and bed stake headers are used to
control the line configuration and operating mode set-
tings for each channel.
In both Hardware and Host modes, the board may be
configured for E1 75 Ω or E1 120 Ω operating modes. In
both modes binding post connectors provide easy con-
nections between the line interface connections of the
CS61880 and any E1 analyzing equipment, which may
be used to evaluate the CS61880 device. Bed stake
headers allow easy access to each channel's clock and
data I/O digital interface.
Eight LED indictors display the Loss of Signal (LOS)
conditions for each channel during Hardware and Host
modes. An LED indictor is used on the Interrupt pin to in-
dicate a change of state.
Note: Click on any
ORDERING INFORMATION
CS61880-IQ
CDB61880
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
CDB61880
text
in blue to go to cross-references
-40° to 85° C
144-pin LQFP
Evaluation Board
MAR '02
DS450DB1
1
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Related Manuals for Cirrus Logic CS61880
Summary of Contents for Cirrus Logic CS61880
- Page 1 Description Socketed CS61880 Octal Line Interface Unit The CS61880 evaluation board is used to demonstrate the functions of a CS61880 Octal Line Interface Unit in Binding post connectors for power and line either E1 75 Ω or E1 120 Ω.
-
Page 2: Table Of Contents
IN S U C H AP P LIC ATIO N S IS U ND E R STO O D TO BE FU LLY A T TH E C U S TO M E R 'S R ISK . C irrus Logic, C irrus, and the C irrus Logic logo designs are tradem arks of Cirrus Logic, Inc. A ll other brand and product nam es in this docum ent m ay be trade- m arks or service m arks of their respective ow ners. - Page 3 CDB61880 5.1 Choose Parallel Port Settings ..................12 5.2 Access and Configure the Read / Write Registers ............12 5.2.1 Access Configuration Screens ................12 5.2.2 Select Register to Configure ................12 5.3 Loopback /Bits Clock Screen ................... 13 5.4 LOS/AIS/DFM/JA Register Screen .................. 14 5.5 Transmitter Register Screen ....................
-
Page 4: Cdb61880 Evaluation Board Layout
CDB61880 CDB61880 EVALUATION BOARD LAYOUT Figure 1. CDB61880 Board Layout DS450DB1... -
Page 5: Board Component Descriptions
- To measure the current consumption of only source for all E1 modes. the CS61880 device, place a short block on - A BNC connector (labeled J16) provides the Jumper J13 to connect the Vlogic power connection for an external clock source. -
Page 6: Operating Mode Selection
Table 2 are used to place or bypass 1 KΩ protection resistors in series with the The operating mode for the CS61880 can be select- receive line signals (RTIP/RRING). These resis- ed by setting switch S15 to one of the positions... -
Page 7: Clock Edge Selection
S10. Figure 5. In Host mode, switch S10 has no effect on the CS61880 device and should be set to the open (middle) position. H I G H H I G H... -
Page 8: Line Length/Impedance Selection
3 through 7 inside switch block S9 are all the device. Refer to the CS61880 Data Sheet for the set to the closed “LOW” position, the G.772 Non- CBLSEL settings. -
Page 9: Digital Signal Connections
CDB61880 2.13 Digital Signal Connections corresponding receiver has detected a loss of signal condition. Refer to the CS61880 Data Sheet for There are eight fourteen pin bed stake headers (la- LOS conditions. beled J4 through J11) that provide access to the digital signals used to interface with back-end de- 2.15 JTAG Connection... -
Page 10: Host Software Interface
CS61880 software, simply click on the appro- priate CS61880 software icon (Win95 or NT) on Figure 12. Register Bit Box the CD in the CDB61880 kit. The CS61880 soft- ware is used to evaluate the CS61880 device. 4.3 Set All Button Description... -
Page 11: Clear All Button Description
CDB61880 4.3.1 Clear All Button Description The CLR All Button shown Figure 14 is used to set Figure 16. Read All Button all the bits in the corresponding register to 0s. This button is placed to the left of each register that has 4.4 Write Button Description write access. -
Page 12: Cs61880 Configuration Screens
CDB61880 5. CS61880 CONFIGURATION SCREENS 5.1 Choose Parallel Port Settings 5.2 Access and Configure the Read / Write Registers The opening screen shown before in Figure 11 now in Figure 19 is used for the following configu- You also use the opening screen to access the... -
Page 13: Loopback /Bits Clock Screen
CDB61880 5.3 Loopback /Bits Clock Screen - Remote loop back - Analog loop back The Loopback /Bits Clock Register tabbed screen - Digital Loopback shown in Figure 20 allows access to the following - G.703 Bits Clock registers: Figure 20. Loopback/G.703 Bits Clock Selection Screen DS450DB1... -
Page 14: Los/Ais/Dfm/Ja Register Screen
CDB61880 5.4 LOS/AIS/DFM/JA Register Screen - DFM Status - DFM interrupt Status The LOS/AIS/DFM/JA Register tabbed screen - DFM Interrupt Enable shown in Figure 21 allows access to the following - AIS Status registers: - AIS Interrupt Enable - LOS Status - AIS Interrupt Status - LOS Interrupt Enable - JA Error Interrupt Enable... -
Page 15: Transmitter Register Screen
CDB61880 5.5 Transmitter Register Screen - Line Length Channel ID - Line Length Data The Transmitter Register screen shown in - Output Disable. Figure 22 consists of the following registers: NOTE: Some indictor boxes (bits) in the Performance - Automatic TAOS Monitor, Line Length Channel ID, and Line - TAOS Enable Length Data registers are grayed out, this... -
Page 16: Awg Register Screen
Chan Address, Sample Address, and Phase Data - AWG Overflow Interrupt Status input boxes use the values discussed in the AWG - AWG Phase Address section of the CS61880 Data Sheet. - AWG Phase Data. Figure 23. AWG Registers Screen DS450DB1... -
Page 17: Global Control Register Screen
CDB61880 5.7 Global Control Register Screen - Jitter Attenuator - JA FIFO Length Figure 24 shows the Global Control Register - AWG Auto Increment (GCR) screen, The GCR register screen consists of - Raisen the following registers: - Coden - Software reset - Jitter Corner Freq. -
Page 18: Board Configurations
4. Set “HIGH” to enable BITS Clock Recovery function for only Channel #0 in Hardware Mode. 5. Other settings may be used to enter G.772 Non-Intrusive Monitoring in Hardware Mode. Refer to the CS61880 Data Sheet for other settings. 6. Set “LOW” to disable receiver Internal line impedance matching function. The external resistors for all eight receivers must be changed to 9.31 Ω... -
Page 19: E1 120 Ω Mode Setup
CDB61880 6.2 E1 120 Ω Ω Ω Ω Mode Setup Host and Parallel Host operational modes. Before selecting Host mode, the switches in Table 5 Table 5 shows the position of the different switches bold should be set to the position stated. and jumpers used to set up the CDB61880 evalua- tion board to operate in E1 120 Ω... -
Page 20: Evaluation Hints
- A short in the desired position must be placed - When using the CS61880 device in Internal on Jumper J13 to connect the CS61880 to one Match Impedance mode, be sure that the 1 KΩ of the power supply binding post. LED D3 will resistors are not in series with the receivers. - Page 21 • Notes •...
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