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Altera Corporation
July 2010
For technical details on the components in standard hardware system
refer to
Quartus II Handbook Volume 5: Embedded Peripherals.
Communication Interfaces
There are several communication interfaces included in the Nios II
Standard System:
■
JTAG UART
—
Used for Serial communication and debugging Nios
II applications via the on-board USB-Blaster circuitry.
■
—
Serial communication link for general purpose
UART
communications and debug.
■
—
Used to communicate with the touch panel portion of the LCD
SPI
Touchscreen.
■
10/100 Ethernet Controller
Triple-speed Ethernet MAC to communicate with the PHY on the
LCD Multimedia Daughtercard.
■
Video Pipeline
—
data and sync signals to the LCD Touch Panel. It provides high
bandwidth memory access that allows for flicker free display on the
color LCD. A more detailed description of the data flow for the video
pipeline can be found in
The video pipeline is comprised of:
PIO for LCD I
●
the LCD panel for brightness and set the gamma correction
curves.
SPI Touch Panel Controller
●
touch panel ADCs.
Pixel Converter
●
R-G-B-0 data to an 8-bit data stream. This is required because of
the pin-limitation placed on the system by the HSMC connector.
The video data-stream is multiplexed in the FPGA on the
Cyclone III Starter Board and de-multiplexed in the MAX II
device on the LCD Multimedia Daughtercard.
Sync Generator
●
signals for each frame displayed on the LCD touch screen.
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For more information on the video pipeline (pixel
converter and Video Sync Generator) and GPIO
components refer to
Embedded
Development Board Version 1.0.
—
The Ethernet controller uses the
The video pipeline outputs the appropriate pixel
Appendix
A.
2
2
C Controller
—
The I
—
Used to communicate with the
—
Logic block that converts parallel 32-bit
—
Generates the horizontal and vertical sync
Quartus II Handbook Chapter 5
Peripherals.
Nios II Embedded Evaluation Kit, Cyclone III Edition
Nios II Processor Systems
C pins are used to configure
3–6
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