Altera Nios II Embedded Evaluation Kit Cyclone III Edition User Manual page 29

Where to find the Nios II Processor Systems
3–5
Nios II Embedded Evaluation Kit, Cyclone III Edition
System Functions
■
—
PLL The PLL accepts the global input clock source from the
50-MHz on-board oscillator and generates the following clocks
100-MHz CPU Clock
●
100-MHz SSRAM Clock
●
66.5-MHz DDR SDRAM Clock
●
60-MHz Peripheral Clock ("slow peripherals")
●
40-MHz Remote System Update Clock
●
■
System Clock Timer
■
Performance Counter
performance analysis.
■
—
System ID Used to sync the hardware system generation with the
software generation tools.
■
Remote System Update Block
boot-time from the on-board active parallel flash. The Nios II
processor writes reset address of the hardware system stored in flash
for reconfiguration.
■
LED PIO — Output only control block for LED1-LED4
■
—
Pushbutton PIO
pushbuttons.
■
PIO for ID EEPROM (I2C)
EEPROM ID chip which stores information about the board
including the touch panel calibration data and Ethernet MAC
address.
1
The I2C interface is implemented using software and general
purpose I/Os connected to the Nios II Standard System.
Memory Interface
There are four different types of on-board memory or storage devices.
The memory controllers for three of these devices are provided as part of
Altera's IP Suite and include:
■
SSRAM Controller
■
DDR SDRAM Controller
■
CFI Flash Controller
■
SD Card
1
The controller, API, and FAT File System for the SD-Card used
in the Nios II Standard System is provided under license
agreement by El Camino (http://www.elcamino.de)
Development Board Version 1.0.
— General purpose system timer.
—
Counter used for debug and system
— Used for automatic configuration at
Input only control block for the on-board
— Used to communicate with the
Altera Corporation
July 2010