Pac Interrupt; Osd Interrupts - Motorola MC68HC05T16 Technical Data Manual

4.2.6

PAC Interrupt

Pulse Accumulator interrupt is enabled when the enable bit, PAIE of PAC Control register is set.
The interrupt service routine address for PAC is specified by the contents of memory location
$FFF2 and $FFF3.
4
PACTL
PAOF - PAC Overflow Interrupt Flag Bit.
1 (set)
0 (clear) –
It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by
writing a "0" to the bit. An interrupt to the CPU is generated if the PAIE bit is set.
PAIE - PAC Interrupt Enable Bit
1 (set)
0 (clear) –
Refer to section 7 for detailed description of Pulse Accumulator.
4.2.7

OSD Interrupts

There are five OSD interrupt sources, VFLBK bit and R0/1/2/3CF bits of OSD Status register, in
the OSD module. VFLB bit will be set whenever the leading edge of vertical flyback pin, VFLBK,
has been detected. An interrupt will occur if the corresponding interrupt enable bit, VFINTE, is set.
Whenever each row terminates its display, RiCF bit will be set and an interrupt will be generated
provided that the corresponding interrupt enable bit, RiINTE is set. The interrupt service routine
address is specified by the contents of memory location $FFFA and $FFFB.
Frame Control 3 and Status
VFINTE - VFLBK interrupt enable
1 (set)
0 (clear) –
MOTOROLA
4-10
Address bit 7
$0E PAOF PAEN PAMOD PAIE
– A PAC overflow from $FF to $00 has occurred.
No PAC overflow has occurred.
– PAC overflow Interrupt enabled.
PAC overflow Interrupt disabled.
Address bit 7
$2B VFINTE MUTE1 MUTE0 VFLB R3CF R2CF R1CF R0CF 0000 0000
– Vertical flyback interrupt enabled.
Vertical flyback interrupt disabled.
RESETS AND INTERRUPTS
bit 6 bit 5 bit 4 bit 3
bit 6 bit 5 bit 4 bit 3
State
bit 2 bit 1 bit 0
on reset
0000 0000
State
bit 2 bit 1 bit 0
on reset
MC68HC05T16
TPG