t
VDDR
VDD
VDD THRESHOLD (TYPICALLY 1-2V)
1
EXTAL PIN
t
oxov
INTERNAL
2
CLOCK
INTERNAL
ADDRESS
2
BUS
INTERNAL
DATA
2
BUS
RESET
NOTES:
1. EXTAL is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
MC68HC05T16
t
cyc
FFFE
FFFF
NEW
NEW
PCL
PCH
Figure 4-1 Power-On Reset and RESET Timing
RESETS AND INTERRUPTS
4064 t
cyc
NEW PC
FFFE
FFFE
OP
PCH
CODE
t
=1.5t
RL
CYC
3
FFFF
NEW PC
OP
PCL
CODE
TPG
MOTOROLA
4-3
4