Motorola MC68HC05T16 Technical Data Manual page 15

Figure
Number
1-1 MC68HC05T16/MC68HC705T16 Block Diagram ..................................................1-2
2-1 Pin Assignments for 56-pin SDIP package.............................................................2-3
2-2 Parallel Port I/O Circuitry ........................................................................................2-5
3-1 MC68HC05T16/MC68HC705T16 Memory Map ....................................................3-2
4-1 Power-On Reset and RESET Timing......................................................................4-3
4-2 Interrupt Stacking Order .........................................................................................4-4
4-3 External Interrupt Circuit and Timing ......................................................................4-7
5-1 Programmable Timer Block Diagram......................................................................5-2
5-2 Timer State Timing Diagram for Reset ...................................................................5-8
5-3 Timer State Timing Diagram for Input Capture .......................................................5-8
5-4 Timer State Timing Diagram for Output Compare ..................................................5-9
5-5 Timer State Diagram for Timer Overflow ................................................................5-9
6-1 M-Bus Interface Block Diagram ..............................................................................6-2
6-2 M-Bus Transmission Signal Diagram ......................................................................6-3
6-3 Clock Synchronization ............................................................................................6-5
8-1 7-Bit PWM Output Waveform..................................................................................8-2
8-2 14-Bit PWM Output Waveform................................................................................8-3
9-1 OSD Character and Row Structure ........................................................................9-4
9-2 Reserved Character ROM Codes...........................................................................9-5
9-3 Color Palette Organization......................................................................................9-6
9-4 Output Signal Timing Diagram - Without Background ............................................9-10
9-5 Output Signal Timing Diagram - With Background .................................................9-11
9-6 Resolution of Overlap among Rows .......................................................................9-11
9-7 Fading Out Sequence.............................................................................................9-16
10-1 ADC Block Diagram..............................................................................................10-1
11-1 Programming model .............................................................................................11-1
11-2 Stacking order ......................................................................................................11-2
13-1 Flowchart of Mode Entering .................................................................................13-1
13-2 Self-Check Mode Timing ......................................................................................13-2
13-3 MC68HC05T16 Self-Test Circuit ..........................................................................13-3
14-1 M-Bus Timing Diagram .........................................................................................14-4
15-1 56-pin SDIP Mechanical Dimensions ...................................................................15-1
MC68HC05T16
LIST OF FIGURES
TITLE
Page
Number
TPG
MOTOROLA
vii