Motorola MC68HC05T16 Technical Data Manual page 51

INTERNAL
PROCESSOR
CLOCK
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
$F455
(16 BIT)
OUTPUT COMPARE
REGISTER
COMPARE REGISTER
LATCH
OUTPUT COMPARE
Flag and TCMP1, 2
Note: 1. The CPU write to the compare registers may take place at any time, but a compare only occurs at
the timer state T01. Thus a 4-cycle difference may exist between the write to the compare register
and the actual compare.
2. The output compare flag is set at the timer state T11 that follows the comparison match ($F547 in
this example).
Figure 5-4 Timer State Timing Diagram for Output Compare
INTERNAL
PROCESSOR
CLOCK
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
$FFFE
(16 BIT)
TIMER
OVERFLOW
FLAG (TOF)
Note:
The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000).
It is cleared by a read of the timer status register during the internal processor
clock high time followed by a read of the counter low register.
Figure 5-5 Timer State Diagram for Timer Overflow
MC68HC05T16
$F456 $F457
Note 1
CPU writes $F457
Note 1
Note 2
$FFFF $0000
TIMERS
$F458 $F459
$F457
$0001 $0002
MOTOROLA
5
TPG
5-9