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Function
Increment
Decrement
Clear
Complement
Negate (two's complement)
Rotate left through carry
Rotate right through carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
MC68HC05L1
Table 11-5 Read/modify/write instructions
Inherent
Inherent
(A)
INC
4C
1
3
5C
DEC
4A
1
3
5A
CLR
4F
1
3
5F
COM
43
1
3
53
NEG
40
1
3
50
ROL
49
1
3
59
ROR
46
1
3
56
LSL
48
1
3
58
LSR
44
1
3
54
ASR
47
1
3
57
TST
4D
1
3
5D
MUL
42
1
11
Table 11-6 Control instructions
Function
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
CPU CORE AND INSTRUCTION SET
Addressing modes
Indexed
Direct
(X)
offset)
1
3
3C
2
5
7C
1
3
3A
2
5
7A
1
3
3F
2
5
7F
1
3
33
2
5
73
1
3
30
2
5
70
1
3
39
2
5
79
1
3
36
2
5
76
1
3
38
2
5
78
1
3
34
2
5
74
1
3
37
2
5
77
1
3
3D
2
4
7D
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
1
9
9C
1
2
9D
1
2
8E
1
2
8F
1
2
Indexed
(no
(8-bit
offset)
1
5
6C
2
6
1
5
6A
2
6
1
5
6F
2
6
1
5
63
2
6
1
5
60
2
6
1
5
69
2
6
1
5
66
2
6
1
5
68
2
6
1
5
64
2
6
1
5
67
2
6
1
4
6D
2
5
TPG
MOTOROLA
11-7
11
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