Motorola MC68HC05T16 Technical Data Manual page 97

Operation
Description
Function
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
Add memory and carry to A
Subtract memory
Subtract memory from A
with borrow
AND memory with A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A
with memory
Arithmetic compare X
with memory
Bit test memory with A
(logical compare)
Jump unconditional
Jump to subroutine
MC68HC05L1
Table 11-1 MUL instruction
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
Condition
codes
Source
Addressing mode
Form
Inherent
Table 11-2 Register/memory instructions
Immediate Direct
LDA A6 2 2 B6 2
LDX AE 2 2 BE 2
STA B7 2
STX BF 2
ADD AB 2 2 BB 2
ADC A9 2 2 B9 2
SUB A0 2 2 B0 2
SBC A2 2 2 B2 2
AND A4 2 2 B4 2
ORA AA 2 2 BA 2
EOR A8 2 2 B8 2
CMP A1 2 2 B1 2
CPX A3 2 2 B3 2
BIT A5 2 2 B5 2
JMP BC 2
JSR BD 2
CPU CORE AND INSTRUCTION SET
X:A ← X*A
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
C : Cleared
MUL
Cycles Bytes Opcode
11 1 $42
Addressing modes
Indexed
Extended (no
offset)
3 C6 3 4 F6 1
3 CE 3 4 FE 1
4 C7 3 5 F7 1
4 CF 3 5 FF 1
3 CB 3 4 FB 1
3 C9 3 4 F9 1
3 C0 3 4 F0 1
3 C2 3 4 F2 1
3 C4 3 4 F4 1
3 CA 3 4 FA 1
3 C8 3 4 F8 1
3 C1 3 4 F1 1
3 C3 3 4 F3 1
3 C5 3 4 F5 1
2 CC 3 3 FC 1
5 CD 3 6 FD 1
Indexed Indexed
(8-bit (16-bit
offset) offset)
3 E6 2 4 D6 3 5
3 EE 2 4 DE 3 5
4 E7 2 5 D7 3 6
4 EF 2 5 DF 3 6
3 EB 2 4 DB 3 5
3 E9 2 4 D9 3 5
3 E0 2 4 D0 3 5
3 E2 2 4 D2 3 5
3 E4 2 4 D4 3 5
3 EA 2 4 DA 3 5
3 E8 2 4 D8 3 5
3 E1 2 4 D1 3 5
3 E3 2 4 D3 3 5
3 E5 2 4 D5 3 5
2 EC 2 3 DC 3 4
5 ED 2 6 DD 3 7
TPG
MOTOROLA
11-5
11