Frame Control 3 And Status Register - Motorola MC68HC05T16 Technical Data Manual

HFPOL - HFLBK input polarity select
1 (set) – Horizontal flyback signal at HFLBK is active low.
0 (clear) – Horizontal flyback signal at HFLBK is active high.
HTPOL - FBKG output polarity select
1 (set) – HTONE (half tone) output pin is active low.
0 (clear) – HTONE (half tone) output pin is active high.
The HTONE output pin is shared with port pin PF3. If HTONE is disabled, HTPOL will have no
effect.
FBPOL - FBKG output polarity select
1 (set) – FBKG (fast blanking) output pin is active low.
0 (clear) – FBKG (fast blanking) output pin is active high.
RGBPOL - RGB output polarity select
1 (set) – RBG output pins are active low.
0 (clear) – RGB output pins are active high.
IPOL - I output polarity select
1 (set) – I (intensity) output pin is active low.
0 (clear) – I (intensity) output pin is active high.
9.5.3

Frame Control 3 and Status Register

Address bit 7
$2B VFINTE
Bits 7 to 5 are control bits whereas bits 4 to 0 are status bits associated with interrupt. A status bit
is cleared by writing a 0 to that bit. Care must be taken while clearing a status bit: make sure the
MC68HC05T16
On-Time
BR1 BR0
(frames)
0 0
0 1
1 0
1 1
bit 6 bit 5 bit 4
MUTE1 MUTE0 VFLB
ON-SCREEN DISPLAY
Off-Time
(frames)
24 8
48 16
96 32
192 64
bit 3 bit 2 bit 1
R3CF R2CF R1CF
State
bit 0
on reset
R0CF 0000 0000
TPG
MOTOROLA
9-17
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