Philips 32PF9968/10 Service Manual page 142

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EN 142 9. Q523.1U LA
Block diagram
D
Vin
PWM GENERATOR
& MOSFET DRIVER
GND
Figure 9-8 Block diagram synchronous buck converter.
The advantage of a "synchronous buck converter" over a
"classical buck converter" is its better efficiency (about 90%).
The difference between the two is that in a synchronous buck
converter the "low -side" diode is replaced by a MOSFET TS2
(item 7U03). This, because the voltage drop across a MOSFET
is smaller than the forward voltage drop of a diode.
This second MOSFET TS2 conducts current during the "off"
times of the first MOSFET TS1 (item 7U01 at the input side).
The upper MOSFET TS1 conducts, to transfer energy from the
input to the inductor L and load R
1
TS2 conducts to circulate the inductor current (free wheel). The
synchronous PWM control block regulates the output voltage
by modulating the conduction intervals of the upper and lower
MOSFETs.
PWM Generator and MOSFET Drivers
This circuit is a one-chip solution (item 7U00). It contains all the
circuitry for two independent buck regulators (3V3 and 1V2).
The MOSFETs 7U01, 7U06, 7U03 and 7U08 are the switching
transistors, they are conducting alternatively.
• Time sequence 1: 7U01/7U06 is conducting; energy is
stored in coil 5U01/5U02. The current is flowing from the
+12VSW power supply source.
• Time sequence 2: 7U01/7U06 is blocked; energy is stored
in coil 5U01/5U02.
• Time sequence 3: 7U03/7U08 is conducting, and the
current circuit is now closed via 7U03/7U06, 5U01, 5U02,
2U09/2U94/2U21/2U90/2U921/2U92, and the load. So the
energy stored in the coil during time sequence T1 is
consumed during sequence T3. The signal on the gate
7U03/7U08 is 180 degrees turned compared with the
signal on the gate 7U01/7U06.
Voltage Booster
This circuit is build around capacitors 2U29 and 2U26, resistor
3U62/3UA1, diodes 6U06 and 6U04, and transistor 7U07.
It generates the +18 V boost voltage on pin 4 of item 7U00, to
drive the "high-side" power MOS-FET 7U01/7U06. The voltage
is generated only during normal operation of the converter;
therefore, any drop in its value means an internal fault
condition, which is sensed by the internal protection circuit.
The AC component of the voltage on the source of transistor
7U01/7U06 is rectified by the diodes and added to the input
voltage, resulting into the boost voltage. The resistor 3U62/
3UA1 limits the peak current through the rectifier diodes.
Over-current Detection
Over-current detection is done via components 3U33, 3U26,
3U27, 3U31, and 2U18 for the 3.3 V converter and 3U43, 3U36,
3U37, 3U40, and 2U20 for the 1.2 V converter.
Under-voltage Detection
There is an additional circuit (7U10 and 7U11) to switch "off"
the 3.3 V converter in case the +12VS drops below 9 V.
Service Tips
• When a power MOS-FET is found defective, replace the
other power MOS-FET as well.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
TS1
L1
S
G
TS2
D
FB
C1
G
S
F_15400_005.eps
130707
, while the lower MOSFET
L
• For a normal operation of the converter, it is important to
check the switching frequency and the value of the boost
voltage.
Vout
9.5 Front-End
Refer to figure "Architecture of TV520 platform" earlier in this
chapter for details. Refer also to block diagrams B03A, B03B
and B04.
GND
9.5.1 Device specifications
Tuner (TD1736)
The tuner has the following specifications:
• Hybrid tuner with asymmetrical IF output.
• Down conversion from RF to IF frequency (picture carrier
46.125 MHz at analog reception, centre frequency 44 MHz
at digital reception).
• AGC control signal is coming from master IF device
(TDA9897).
• Only 5 V external supply needed (internal DC-DC
conversion to 3.3 V).
• Internal PLL synthesizer (XTAL running on f = 4 MHz).
The application in this chassis is as follows:
2
• I C address C0.
• FM trap, no broadband AGC, no IF section, no OOB.
2
• I C communication buffered via MUX.
• 4 MHz output that is being used by Master IF.
• Gain to obtain optimized Master IF input level; control
signal is coming from Master IF.
• Output level ca. 110 dBμV (for strong input signal).
Master IF (TDA9897)
The Master IF device has the following specifications:
• CVBS output.
• SIF/LIF output.
The application in this chassis is as follows:
2
• I C address 0x86.
• Down conversion from IF to low-IF frequency (4 MHz
centre frequency).
• Advanced filtering (for further rejection of adjacent
channels).
• Gain to obtain optimized channel decoder level. Control
signal is coming from channel decoder.
SAW filter
X6931D
• Analog sound for NTSC-M.
• ATSC/QAM (digital reception sound and video).
For digital reception. the application in this chassis is as
follows:
• Rejection of adjacent channels.
• Switching is done by Master IF (3 inputs).
X6767D
• Analog video NTSC.
Channel decoder (TDA10060)
The channel decoder has the following specifications:
2
• I C address 0x1E.
• Decoding from low-IF to MPEG transport stream.
• During decoding: de-modulation, de-interleaving and error
correction.
• External 54 MHz Xtal required.
• AGC monitor.
9.5.2 Analog signal processing (front-end)
Refer to figure "NTSC video broadcast reception block
diagram" and "NTSC audio broadcast reception block diagram"
for details of analog signal processing.