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General-purpose
Register File
1004D–09/01
Figure 7 shows the structure of the 32 general-purpose registers in the CPU.
Figure 7. AVR CPU General-purpose Working Registers
General
Purpose
Working
Registers
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND and
OR and all other operations between two registers or on a single register apply to the
entire register file.
As shown in Figure 7, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although the register file
is not physically implemented as SRAM locations, this memory organization provides
great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to
index any register in the file.
AT90S/LS2323/2343
7
0
Addr.
R0
$00
R1
$01
R2
$02
...
R13
$0D
R14
$0E
R15
$0F
R16
$10
R17
$11
...
R26
$1A
R27
$1B
R28
$1C
R29
$1D
R30
$1E
R31
$1F
X-register low byte
X-register high byte
Y-register low byte
Y-register high byte
Z-register low byte
Z-register high byte
9
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