Advertisement
Power-on Reset
1004D–09/01
Table 4. Reset Characteristics (V
Symbol
Parameter
Power-on Reset Threshold Voltage, rising
(1)
V
POT
Power-on Reset Threshold Voltage, falling
V
RESET Pin Threshold Voltage
RST
Reset Delay Time-out Period AT90S/LS2323
t
TOUT
FSTRT Programmed
Reset Delay Time-out Period AT90S/LS2323
t
TOUT
FSTRT Unprogrammed
t
Reset Delay Time-out Period AT90S/LS2343
TOUT
Note:
1. The Power-on Reset will not work unless the supply voltage has been below V
(falling).
Table 5. Reset Characteristics (V
Symbol
Parameter
Power-on Reset Threshold Voltage, rising
(1)
V
POT
Power-on Reset Threshold Voltage, falling
V
RESET Pin Threshold Voltage
RST
Reset Delay Time-out Period AT90S/LS2323
t
TOUT
FSTRT Programmed
Reset Delay Time-out Period AT90S/LS2323
t
TOUT
FSTRT Unprogrammed
t
Reset Delay Time-out Period AT90S/LS2343
TOUT
Note:
1. The Power-on Reset will not work unless the supply voltage has been below V
(falling).
The AT90S2323/2343 is designed for use in systems where it can operate from the
internal RC oscillator (AT90S/LS2343), on-chip oscillator (AT90S/LS2323), or in appli-
cations where a clock signal is provided by an external clock source. After V
reached V
, the device will start after the time t
POT
is provided by an external clock source, the clock must not be applied until V
reached the minimum voltage defined for the applied frequency.
For AT90S2323, the user can select the start-up time according to typical oscillator
start-up. The number of WDT oscillator cycles used for each time-out is shown in
Table 6. For AT90S2343, the start-up time is one Watchdog cycle only. The frequency
of the Watchdog oscillator is voltage-dependent as shown in "Typical Characteristics" on
page 49.
Table 6. Number of Watchdog Oscillator Cycles
FSTRT
Programmed
Unprogrammed
AT90S/LS2323/2343
= 5.0V)
CC
= 3.0V)
CC
TOUT
Time-out at V
= 5V
CC
1.1 ms
16.0 ms
Min
Typ
Max
1.0
1.4
1.8
0.4
0.6
0.8
0.6 V
CC
1.0
1.1
1.2
11.0
16.0
21.0
11.0
16.0
21.0
Min
Typ
Max
1.0
1.4
1.8
0.4
0.6
0.8
0.6 V
CC
2.0
2.2
2.4
22.0
32.0
42.0
22.0
32.0
42.0
(see Figure 25). If the clock signal
Number of WDT Cycles
1K
16K
Units
V
V
V
ms
ms
µs
POT
Units
V
V
V
ms
ms
µs
POT
has
CC
has
CC
21
Advertisement
