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Watchdog Reset
MCU Status Register –
MCUSR
1004D–09/01
When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle
duration. On the falling edge of this pulse, the delay timer starts counting the Time-out
period t
. Refer to page 30 for details on operation of the Watchdog.
TOUT
Figure 28. Watchdog Reset during Operation
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit
7
$34 ($54)
–
Read/Write
R
Initial Value
0
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and always read as zero.
• Bit 1 – EXTRF: External Reset Flag
After a Power-on Reset, this bit is undefined (X). It will be set by an External Reset. A
Watchdog Reset will leave this bit unchanged.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave
this bit unchanged.
To summarize, Table 7 shows the value of these two bits after the three modes of reset.
Table 7. PORF and EXTRF Values after Reset
Reset Source
Power-on Reset
External Reset
Watchdog Reset
To make use of these bits to identify a reset condition, the user software should clear
both the PORF and EXTRF bits as early as possible in the program. Checking the
PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before
an External or Watchdog Reset occurs, the source of reset can be found by using the
following truth table, Table 8.
6
5
4
–
–
–
R
R
R
0
0
0
PORF
1
Unchanged
Unchanged
AT90S/LS2323/2343
3
2
1
–
–
EXTRF
PORF
R
R
R/W
0
0
See Bit Description
EXTRF
Undefined
Unchanged
0
MCUSR
R/W
1
23
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