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I/O Memory
1004D–09/01
Figure 23. On-chip Data SRAM Access Cycles
System Clock Ø
Address
Data
WR
Data
RD
The I/O space definition of the AT90S2323/2343 is shown in Table 2.
Table 2. AT90S2323/2343 I/O Space
Address Hex
Name
$3F ($5F)
SREG
$3D ($5D)
SPL
$3B ($5B)
GIMSK
$3A ($5A)
GIFR
$39 ($59)
TIMSK
$38 ($58)
TIFR
$35 ($55)
MCUCR
$34 ($54)
MCUSR
$33 ($53)
TCCR0
$32 ($52)
TCNT0
$21 ($41)
WDTCR
$1E ($3E)
EEAR
$1D ($3D)
EEDR
$1C ($3C)
EECR
$18 ($38)
PORTB
$17 ($37)
DDRB
$16 ($36)
PINB
Note:
Reserved and unused locations are not shown in the table.
All AT90S2323/2343 I/Os and peripherals are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general-
purpose working registers and the I/O space. I/O registers within the address range $00
- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer
to the instruction set section for more details. When using the I/O-specific commands IN
AT90S/LS2323/2343
T1
T2
Prev. Address
Address
Function
Status REGister
Stack Pointer Low
General Interrupt MaSK register
General Interrupt Flag Register
Timer/Counter Interrupt MaSK register
Timer/Counter Interrupt Flag register
MCU Control Register
MCU Status Register
Timer/Counter0 Control Register
Timer/Counter0 (8-bit)
Watchdog Timer Control Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register
Data Register, Port B
Data Direction Register, Port B
Input Pins, Port B
T3
T4
17
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