Motorola MC68341 User Manual page 16

65. Corrections to 8/16-Bit DMA Control Logic
On page 11-10, the logic driving OE on the 74F245 in Figure 11-14 should be corrected as shown below. Al-
though not detailed, the byte enables for the memory block should be controlled during reads to prevent con-
tention between the upper and lower bytes of the data bus when D7-D0 is muxed to the upper data byte.
Figure 11-14. Circuit For Interfacing 8-Bit Device to 16-Bit Memory
66. X1 and BSW Input Levels
On page 12-5, the Clock Input High Voltage spec also applies to the X1 and BSW inputs.
67. Operating IDD Limits
On page 12-5, the spec operating (RUN) currents are shown in the following table:
Product
68341FT16V
68341FT16
68341FT25
68. Input Clock Duty Cycle in External Clock w/PLL mode
On page 12-7, External Clock With PLL Mode: The input clock 20/80% duty cycle for external clock with PLL
mode can be used when the VCO is not turned off during LPSTOP. During LPSTOP with the VCO turned off,
the input clock is used for clocking the SIM, and must meet the tighter duty cycle requirements outlined for
External Clock Mode Without PLL.
69. Clock Skew Notes
12-7, External Clock With PLL Mode, Clock Input to CLKOUT Skew: Clock skew is measured from the falling
MOTOROLA
DEVICE
R/W
A0
MC68341
DACKx
in Single-Address DMA Mode
Frequency
16.78MHz 95mA@3.6V
16.78MHz 150mA@5.25V
25.16MHz 210mA@5.25V
MC68341 USER'S MANUAL ADDENDUM
D15–D8
B
T/R
74F245
OE
A
D7–D0
Max Idd Typical IDD (25°C)
68mA@3.3V
121mA@5.0V
175mA@5.0V
MEMORY
16