Source Of Described Problem - Adc Design; Figure 37. Implementation Of Sampling Switch - ST STM32 Application Note

AN2834
U = 4096 LSB
max
U = 0.5 LSB
lsb
C
=
ext
( ⋅ )
t R C
= –
C in sh
3.4.4

Source of described problem - ADC design

The following sections list some possible causes for the charging of the internal sampling
capacitor C
design are mentioned.
Parasitic switch capacitance effect
The sampling switch inside ADC sampling circuit (see
sample and hold switch (S
Figure 37):
The switch is controlled by the gate voltages of transistors (inverted signal on PMOS
transistor). This design is a standard bidirectional switch (for rail to rail range of input U
voltages). Both transistors have parasitic capacitances between gate and source.
If those capacitances are charged (close to the switch), then their charge can be transferred
to the sampling capacitor (see
..... ADC property
..... required precision
U
max
, ⋅ ,
1 58 C 1 58
------------- -
=
sh
U
lsb
C U
sh max
⋅
In 1
---------- - ------------- -
– =
C U
ext lsb
. This is not an exhaustive list; only the main possible sources of the ADC
sh
) is designed as 2 transistors (PMOS and NMOS, see
1

Figure 37. Implementation of sampling switch

4096
⋅ ⋅ ≈
16pF 207nF
------------ -
0.5
( ⋅ ) ⋅
150kΩ 220nF In 1
–
Figure 38).
DocID15067 Rev 3
How to get the best ADC accuracy
⇒
220nF
16pF 4096
≈
29891μs
---------------- - ------------ -
–
220nF 0.5
Figure 33) is not ideal. In reality the
⇒
30ms
in
45/49
48