Minimizing Additional Errors; Figure 35. Effect Of Sampling Time Extension - ST STM32 Application Note

AN2834
3.4.3

Minimizing additional errors

Workaround for high impedance sources
To solve the additional error problem, the sampling time (T
configuring ADC settings in MCU firmware, so that the C
source impedance R
sampling time. To calculate the sampling time cycles, use this formula (for a maximum error
of 1/2 LSB, see also
The ADC clock (f
increases the sampling time.
If the maximum register value of the sampling time (T
is still present, you need a more complex solution which is applicable also for
measurements of source with extra high internal impedance (see
extra high impedance
Note that for this application you must take into account not only the internal sampling
capacitance, but also any external parasitic capacitance (in parallel to C
capacitance or PCB path capacitance.
Do not add any external capacitor (C
workaround. Its capacity will increase the timing constant (R
will remain.
. The time constant (R
in
Section 3.2.6):
≥ ⋅ ( ⋅
T f R
S ADC in
) is another important factor, since slowing down the ADC clock
ADC

Figure 35. Effect of sampling time extension

sources).
ext
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How to get the best ADC accuracy
) can be increased by
S
charge is discharged through the
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in sh
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C ln 2 cycles
sh
) setting is reached and the problem
S
) to the input pin when applying this above
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Section : Workaround for
), such as pin
ext
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sh ext
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