Explanation Of The Behavior; Figure 33. Adc Simplified Schematic Of Input Stage - Sample And Hold Circuit; Figure 34. Adc Input Pin Noise Spikes From Internal Charge During Sampling Process - ST STM32 Application Note

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3.4.2

Explanation of the behavior

The explanation of this additional pin noise and additional measurement error (in case a
signal source with high internal impedance is used) comes from the internal ADC structure:
its input sampling circuit.
Figure 33

Figure 33. ADC simplified schematic of input stage - sample and hold circuit

The spikes (noise) present on ADC input pin during conversions are related to the sampling
switch (S
capacitor C
starts discharging through the source impedance (R
end of the sampling time (t
voltage remains on the capacitor C
(t ) is too short, the remaining voltage does not drop under 0.5 LSB and ADC measurement
S
shows an additional error.

Figure 34. ADC input pin noise spikes from internal charge during sampling process

Note that a non-zero external capacitance C
during conversion time the pin capacitance is discharged through source impedance R
40/49
shows a simplified schematic of the input stage (sample and hold circuit).
). If the switch is closed, some charge (coming from the sample and hold
1
or caused by another effect) is transferred to the input pin. Then this charge
sh
) when the switch S
S
Figure 34
in
is opened. The remaining undischarged
1
and ADC measures this voltage. If the sampling time
sh
illustrates this process.
(parasitic pin capacitance) also exists, so
ext
DocID15067 Rev 3
). The discharge process ends at the
AN2834
.
in