Bit Fields - Texas Instruments TMS320C67 DSP Series Programmer's Reference Manual

Glossary
G
H
I
C-4
flag: A binary status indicator whose state indicates whether a particular
condition has occurred or is in effect.
frame: An 8-word space in the cache RAMs. Each fetch packet in the cache
resides in only one frame. A cache update loads a frame with the re-
quested fetch packet. The cache contains 512 frames.
global interrupt enable bit (GIE): A bit in the control status register (CSR)
that is used to enable or disable maskable interrupts.
HAL: Hardware abstraction layer of the CSL. The HAL underlies the service
layer and provides it a set of macros and constants for manipulating the
peripheral registers at the lowest level. It is a low-level symbolic interface
into the hardware providing symbols that describe peripheral registers/
bitfields and macros for manipulating them.
host: A device to which other devices (peripherals) are connected and that
generally controls those devices.
host port interface (HPI): A parallel interface that the CPU uses to commu-
nicate with a host processor.
HPI: See host port interface; see also HPI module.
index: A relative offset in the program address that specifies which of the
512 frames in the cache into which the current access is mapped.
indirect addressing: An addressing mode in which an address points to
another pointer rather than to the actual data; this mode is prohibited in
RISC architecture.
instruction fetch packet: A group of up to eight instructions held in memory
for execution by the CPU.
internal interrupt: A hardware interrupt caused by an on-chip peripheral.
interrupt: A signal sent by hardware or software to a processor requesting
attention. An interrupt tells the processor to suspend its current opera-
tion, save the current task status, and perform a particular set of instruc-
tions. Interrupts communicate with the operating system and prioritize
tasks to be performed.
interrupt service fetch packet (ISFP): A fetch packet used to service inter-
rupts. If eight instructions are insufficient, the user must branch out of this
block for additional interrupt service. If the delay slots of the branch do not
reside within the ISFP, execution continues from execute packets in the
next fetch packet (the next ISFP).