Dspf_Sp_Fir_Gen - Texas Instruments TMS320C67 DSP Series Programmer's Reference Manual

DSPF_sp_fir_gen

Algorithm
Special Requirements
Implementation Notes
4-40
This is the C equivalent for the assembly code. Note that the assembly code
is hand optimized and restrictions may apply.
void DSPF_sp_fir_gen(const float *x, const float *h, float *
restrict r,
int nh, int nr)
{
int i, j;
float sum;
for(j=0; j < nh; j++)
{
sum = 0;
for(i=0; i < nr; i++)
{
sum += x[i+j] * h[i];
}
r[j] = sum;
}
}
-
Little Endian is assumed for LDDW instructions.
-
The number of coefficients must be greater than or equal to 4.
-
The number of outputs must be greater than or equal to 4
-
LDDW instructions are used to load two SP floating-point values simulta-
neously for the x and h arrays.
-
The outer loop is unrolled 4 times.
-
The inner loop is unrolled 2 times and software pipelined.
-
The variables prod1, prod3, prod5, and prod7 share A9.
The variables prod0, prod2, prod4, and prod6 share B6.
The variables sum1, sum3, sum5, and sum7 share A7.
The variables sum0, sum2, sum4, and sum6 share B7.
This multiple assignment is possible since the variables are always read
just once on the first cycle that they are availble.
-
The first 8 cycles of the inner loop prolog are conditionally scheduled in
parallel with the outer loop. This increases the code size by 14 words, but
improves the cycle time.