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Texas Instruments TMS320DM357 User Manual

Texas Instruments TMS320DM357 User Manual

Dmsoc enhanced direct memory access (edma3) controller
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TMS320DM357 DMSoC Enhanced Direct
Memory Access (EDMA3) Controller
User's Guide
Literature Number: SPRUG34
November 2008

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  • Page 1 TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA3) Controller User's Guide Literature Number: SPRUG34 November 2008...
  • Page 2 SPRUG34 – November 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ..........................Preface ......................Introduction ........................Overview ........................Features ..................Terminology Used in This Document ....................EDMA3 Architecture ....................... Functional Overview ................2.1.1 EDMA3 Controller Block Diagram ..............2.1.2 EDMA3 Channel Controller (EDMA3CC) ............... 2.1.3 EDMA3 Transfer Controller (EDMA3TC) ....................Types of EDMA3 Transfers ..................
  • Page 4 www.ti.com ......................2.10 Event Queue(s) ............. 2.10.1 DMA/QDMA Channel to Event Queue Mapping ................... 2.10.2 Queue RAM Debug Visibility ..................2.10.3 Queue Resource Tracking ................... 2.10.4 Performance Considerations ................2.11 EDMA3 Transfer Controller (EDMA3TC) ....................2.11.1 Architecture Details ....................2.11.2 Error Generation ....................
  • Page 5 www.ti.com ....................4.3.7 QDMA Registers ................ EDMA3 Transfer Controller Control Registers ............... 4.4.1 Peripheral Identification Register (PID) ..............4.4.2 EDMA3TC Configuration Register (TCCFG) ............. 4.4.3 EDMA3TC Channel Status Register (TCSTAT) ....................4.4.4 Error Registers ................4.4.5 Read Rate Register (RDRATE) .................
  • Page 6 www.ti.com List of Figures ..................EDMA3 Controller Block Diagram ............. EDMA3 Channel Controller (EDMA3CC) Block Diagram ............. EDMA3 Transfer Controller (EDMA3TC) Block Diagram ................. Definition of ACNT, BCNT, and CCNT ............A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .............
  • Page 7 www.ti.com ................4-19 QDMA Event Missed Register (QEMR) ..............4-20 QDMA Event Missed Clear Register (QEMCR) ................... 4-21 EDMA3CC Error Register (CCERR) ............... 4-22 EDMA3CC Error Clear Register (CCERRCLR) ..................4-23 Error Evaluation Register (EEVAL) ............. 4-24 DMA Region Access Enable Register for Region m (DRAEm) ..........
  • Page 8 www.ti.com ..................4-72 Error Details Register (ERRDET) ............... 4-73 Error Interrupt Command Register (ERRCMD) ..................4-74 Read Rate Register (RDRATE) ................4-75 Source Active Options Register (SAOPT) ..............4-76 Source Active Source Address Register (SASRC) ................4-77 Source Active Count Register (SACNT) ..............
  • Page 9 www.ti.com List of Tables ..................EDMA3 Parameter RAM Contents ................EDMA3 Channel Parameter Description ..................Dummy and Null Transfer Request ........Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ................EDMA3 Channel Synchronization Events ..............Expected Number of Transfers for Non-Null Transfer ................
  • Page 10 www.ti.com ................ 4-34 Event Register High (ERH) Field Descriptions ............... 4-35 Event Clear Register (ECR) Field Descriptions .............. 4-36 Event Clear Register High (ECRH) Field Descriptions ................. 4-37 Event Set Register (ESR) Field Descriptions ..............4-38 Event Set Register High (ESRH) Field Descriptions ..............
  • Page 11 www.ti.com ..... 4-85 Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ....4-86 Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ..........4-87 Destination FIFO Options Register (DFOPTn) Field Descriptions ........4-88 Destination FIFO Source Address Register (DFSRCn) Field Descriptions ...........
  • Page 12 List of Tables SPRUG34 – November 2008 Submit Documentation Feedback...

  • Page 13: Preface

    Preface SPRUG34 – November 2008 Read This First About This Manual Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 14 User's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards.
  • Page 15 SPRUG39 — TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describes the video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller, resizer, histogram, and hardware 3A (H3A) statistic generator.
  • Page 16 Read This First SPRUG34 – November 2008 Submit Documentation Feedback...

  • Page 17: Introduction

    Introduction This document describes the features and operations of the enhanced direct memory access (EDMA3) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 is a high-performance, multichannel, multithreaded DMA controller that allows you to program a wide variety of transfer geometries and transfer sequences.

  • Page 18: Overview

    Overview www.ti.com Overview The enhanced direct memory access (EDMA3) controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. Typical usage includes, but is not limited to: • Servicing software driven paging transfers (for example, from external memory such as SDRAM to internal device memory such as TCM •...

  • Page 19: Terminology Used In This Document

    (See the device data manual to learn more about the CPU on your system.) Device TMS320DM357 DMSoC DMA channel One of the 64 channels that can be triggered by external, manual, and chained events. All DMA channels exist in the EDMA3CC.
  • Page 20 Terminology Used in This Document www.ti.com Term Meaning Link parameter set A PaRAM set that is used for linking. Linking The mechanism of reloading a PaRAM set with new transfer characteristics on completion of the current transfer. Memory-mapped All on-chip memories, off-chip memories, and slave peripherals. These typically rely slave on the EDMA3 (or other master peripheral) to perform transfers to and from them.

  • Page 21: Edma3 Architecture

    Chapter 2 SPRUG34 – November 2008 EDMA3 Architecture This chapter discusses the architecture of the EDMA3 controller....................Topic Page ..............Functional Overview ............Types of EDMA3 Transfers ............Parameter RAM (PaRAM) ............Initiating a DMA Transfer ............ Completion of a DMA Transfer ..........

  • Page 22: Functional Overview

    Functional Overview www.ti.com Functional Overview This section provides a block diagram of the EDMA3 controller, EDMA3 channel controller (EDMA3CC), and EDMA3 transfer controller (EDMA3TC). 2.1.1 EDMA3 Controller Block Diagram Figure 2-1 shows a block diagram for the EDMA3 controller. Figure 2-1. EDMA3 Controller Block Diagram Transfer controllers Channel controller...

  • Page 23: Edma3 Channel Controller (Edma3Cc) Block Diagram

    Functional Overview www.ti.com Figure 2-2. EDMA3 Channel Controller (EDMA3CC) Block Diagram From Peripheral/External Events Event Event Register Queues Parameter (ER/ERH) Event Set 0 Queue 0 Trigger Parameter Event Set 1 Enable Register (EER/EERH) Event EDMA3TC(s) Manual Trigger Register Queue 1 (ESR/ESRH) Chain Parameter...

  • Page 24: Edma3 Transfer Controller (Edma3Tc)

    Functional Overview www.ti.com You may have chosen to receive an interrupt or chain to another channel on completion of the current transfer in which case the EDMA3TC signals completion to the EDMA3CC completion detection logic when the transfer is done. You can alternately choose to trigger completion when a TR leaves the EDMA3CC boundary rather than wait for all the data transfers to complete.

  • Page 25: Types Of Edma3 Transfers

    Types of EDMA3 Transfers www.ti.com When the EDMA3TC is idle and receives its first TR, the TR is received in the DMA program register set, where it transitions to the DMA source active set and the destination FIFO register set immediately. The second TR (if pending from EDMA3CC) is loaded into the DMA program set, ensuring it can start as soon as possible when the active transfer is completed.

  • Page 26: A-Synchronized Transfers

    Types of EDMA3 Transfers www.ti.com 2.2.1 A-Synchronized Transfers In an A-synchronized transfer, each EDMA3 sync event initiates the transfer of the 1st dimension of ACNT bytes, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information for one array only.

  • Page 27: Ab-Synchronized Transfers

    Types of EDMA3 Transfers www.ti.com 2.2.2 AB-Synchronized Transfers In a AB-synchronized transfer, each EDMA3 sync event initiates the transfer of 2 dimensions or one frame. In other words, each event/TR packet conveys information for one entire frame of BCNT arrays of ACNT bytes.

  • Page 28: Parameter Ram (Param)

    Parameter RAM (PaRAM) www.ti.com Parameter RAM (PaRAM) The EDMA3 controller is a RAM-based architecture. The transfer context (source/destination addresses, count, indexes, etc.) for DMA or QDMA channels is programmed in a parameter RAM table within EDMA3CC, referred to as PaRAM. The PaRAM table is segmented into multiple PaRAM sets. Each PaRAM set includes eight 4-byte PaRAM set entries (32-bytes total per PaRAM set), which includes typical DMA transfer parameters such as source address, destination address, transfer counts, indexes, options, etc.

  • Page 29: Param Set

    Parameter RAM (PaRAM) www.ti.com 2.3.1 PaRAM Set Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 2-7 and described in Table 2-2. Each PaRAM set consists of 16-bit and 32-bit parameters. Figure 2-7.

  • Page 30: Edma3 Channel Parameter Description

    Parameter RAM (PaRAM) www.ti.com Table 2-2. EDMA3 Channel Parameter Description Offset Address (bytes) Acronym Parameter Description Channel Options Transfer Configuration Options Channel Source Address The byte address from which data is transferred. ACNT Count for 1st Dimension Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer).

  • Page 31: Edma3 Channel Parameter Set Fields

    Parameter RAM (PaRAM) www.ti.com 2.3.2 EDMA3 Channel Parameter Set Fields 2.3.2.1 Channel Options Parameter (OPT) The 32-bit channel options parameter (OPT) specifies the transfer configuration options. The channel options parameter (OPT) is described in Section 4.2.1. 2.3.2.2 Channel Source Address (SRC) The 32-bit source address parameter specifies the starting byte address of the source.
  • Page 32 Parameter RAM (PaRAM) www.ti.com 2.3.2.8 Source B Index (SRCBIDX) SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between –32 768 and 32 767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array.

  • Page 33: Null Param Set

    Parameter RAM (PaRAM) www.ti.com You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM address that falls in the range of the available PaRAM addresses on the device. A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh.

  • Page 34: Parameter Updates In Edma3Cc (For Non-Null, Non-Dummy Param Set)

    Parameter RAM (PaRAM) www.ti.com Table 2-4 for details and conditions on the parameter updates. A link update occurs when the PaRAM set is exhausted, as described in Section 2.3.7. After the TR is read from the PaRAM (and is in process of being submitted to EDMA3TC), the following fields are updated if needed: •...

  • Page 35: Linking Transfers

    Parameter RAM (PaRAM) www.ti.com 2.3.7 Linking Transfers The EDMA3CC provides a mechanism known as linking, which allows the entire PaRAM set to be reloaded from a location within the PaRAM memory map (for both DMA and QDMA channels). Linking is especially useful for maintaining ping-pong buffers, circular buffering, and repetitive/continuous transfers all with no CPU intervention.

  • Page 36: Linked Transfer

    Parameter RAM (PaRAM) www.ti.com 2.3.7.2 Element Size The EDMA3 controller does not use the concept of element-size and element-indexing. Instead, all transfers are defined in terms of all three dimensions: ACNT, BCNT, and CCNT. An element-indexed transfer is logically achieved by programming ACNT to the size of the element and BCNT to the number of elements that need to be transferred.

  • Page 37: Link-To-Self Transfer

    Parameter RAM (PaRAM) www.ti.com Figure 2-9. Link-to-Self Transfer (a) At initialization PaRAM set 3 Byte OPT X PaRAM address SRC X BCNT X ACNT X 01C0 4000h Parameter set 0 DST X 01C0 4020h Parameter set 1 DSTBIDX X SRCBIDX X 01C0 4040h Parameter set 2 BCNTRLD X...

  • Page 38: Initiating A Dma Transfer

    (EMR.En = 1). Table 2-5 gives an example of the synchronization events associated with each of the programmable DMA channels in the TMS320DM357 device. See the device-specific data manual to determine the event to channel mapping. Table 2-5. EDMA3 Channel Synchronization Events...
  • Page 39 Initiating a DMA Transfer www.ti.com Table 2-5. EDMA3 Channel Synchronization Events (continued) EDMA3 Channel Event Name Event Description PRVUEVT VPSS Preview Event RSZEVT VPSS Resizer Event IMXINT Reserved VLCDINT Reserved ASQINT Reserved DSQINT Reserved 12-15 Unused SPIXEVT SPI Transmit Event SPIREVT SPI Receive Event URXEVT0...
  • Page 40 Initiating a DMA Transfer www.ti.com 2.4.1.2 Manually-Triggered Transfer Request A DMA transfer is initiated by a write to the event set register (ESR) by the CPU (or any EDMA programmer). Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the appropriate event queue, regardless of the state of the EER.En bit.

  • Page 41: Qdma Channels

    Initiating a DMA Transfer www.ti.com 2.4.2 QDMA Channels 2.4.2.1 Autotriggered and Link-Triggered Transfer Request QDMA-based transfer requests are issued when a QDMA event gets latched in the QDMA event register (QER.En = 1). A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when the following occurs: •...

  • Page 42: Completion Of A Dma Transfer

    Completion of a DMA Transfer www.ti.com Completion of a DMA Transfer A parameter set for a given channel is complete when the required number of transfer requests is submitted (based on receiving the number of synchronization events). The expected number of TRs for a non-null/non-dummy transfer is shown in Table 2-6 for both synchronization types along with state of the...

  • Page 43: Normal Completion

    Event, Channel, and PaRAM Mapping www.ti.com 2.5.1 Normal Completion In normal completion mode (TCCMODE = 0 in OPT), the transfer or sub-transfer is considered to be complete when the EDMA3 channel controller receives the completion codes from the EDMA3 transfer controller.

  • Page 44: Dma Channel To Param Mapping

    Event, Channel, and PaRAM Mapping www.ti.com 2.6.1 DMA Channel to PaRAM Mapping The mapping between the DMA channel numbers and the PaRAM sets is a fixed, one-to-one mapping (see Table 2-7). In other words, channel (event) 0 is mapped to PaRAM set 0, channel (event 1) is mapped to PaRAM set 1, etc.

  • Page 45: Edma3 Channel Controller Regions

    EDMA3 Channel Controller Regions www.ti.com Figure 2-10. QDMA Channel to PaRAM Mapping PAENTRY TR WORD QCHMAPn 0000 0000 0000 00 00 0000 011 1 11 Byte Byte address PaRAM PaRAM set address offset 01C0 4000h Parameter set 0 01C0 4020h Parameter set 1 01C0 4040h Parameter set 2...

  • Page 46: Shadow Region Registers

    EDMA3 Channel Controller Regions www.ti.com Table 2-8. Shadow Region Registers DRAEm DRAEHm QRAEn ECRH QEER ESRH QEECR CERH QEESR EERH EECR EECRH EESR EESRH SERH SECR SECRH IERH IECR IECRH IESR IESRH IPRH ICRH Register not affected by DRAE\DRAEH IEVAL Figure 2-11.

  • Page 47: Channel Controller Regions

    Chaining EDMA3 Channels www.ti.com 2.7.2 Channel Controller Regions An EDMA3 transfer is programmed/configured by the ARM. In order to provide autonomous operation for each master, the EDMA3 channel controller allows partitioning of the resources between different masters via the shadow regions. There are four EDMA3 shadow regions (and its associated memory maps). The first shadow region is associated to the EDMA3 programmers (ARM) that have read/write access to the memory-mapped registers of the EDMA3CC.

  • Page 48: Chain Event Triggers

    Chaining EDMA3 Channels www.ti.com Chaining is different from linking (Section 2.3.7). The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained channel (see Section 2.4.1.3 chain-triggered transfer requests).

  • Page 49: Edma3 Interrupts

    The transfer completion interrupts are listed in Table 2-11 and the error interrupts are listed in Table 2-12. For more information on the ARM interrupt controller (AINTC), see the TMS320DM357 DMSoC ARM Subsystem Reference Guide (SPRUG25). Table 2-11. EDMA3 Transfer Completion Interrupts Interrupt Number Name...

  • Page 50: Transfer Complete Code (Tcc) To Edma3Cc Interrupt Mapping

    EDMA3 Interrupts www.ti.com Table 2-13. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping TCC Bits in OPT TCC Bits in OPT (TCINTEN/ITCINTEN = 1) IPR Bit Set (TCINTEN/ITCINTEN = 1) IPRH Bit Set 00 0000b IPR0 10 0000b IPR32/IPRH0 00 0001b IPR1 10 0001b IPR33/IPRH1...

  • Page 51: Edma3 Interrupt Servicing

    EDMA3 Interrupts www.ti.com Figure 2-12. Interrupt Diagram Interrupt pending register (IPR) Interrupt DMA region DMA region DMA region DMA region enable access enable 0 access enable 1 access enable 2 access enable 3 register (DRAE0) (DRAE1) (DRAE2) (DRAE3) (IER) IEVAL0.EVAL IEVAL1.EVAL IEVAL2.EVAL IEVAL3.EVAL...
  • Page 52 EDMA3 Interrupts www.ti.com After servicing the interrupt, the ISR should clear the corresponding bit in IPR/IPRH; therefore, enabling recognition of future interrupts. Only when all IPR/IPRH bits are cleared, the EDMA3CC will assert additional completion interrupts. It is possible that when one interrupt is serviced; many other transfer completions result in additional bits being set in IPR/IPRH, thereby resulting in additional interrupts.
  • Page 53 EDMA3 Interrupts www.ti.com Example 2-1. Interrupt Servicing The pseudo code: 1. Read the interrupt pending register (IPR/IPRH). 2. Perform the operations needed. 3. Write to the interrupt pending clear register (ICR/ICRH) to clear the corresponding IPR/IPRH bit. 4. Read IPR/IPRH again: a.

  • Page 54: Interrupt Evaluation Operations

    EDMA3 Interrupts www.ti.com 2.9.3 Interrupt Evaluation Operations The EDMA3CC has interrupt evaluate registers (IEVAL) in each shadow region. These registers are the only registers in the DMA channel shadow region memory map that are not affected by the settings for the DMA region access enable registers (DRAE/DRAEH).

  • Page 55: Event Queue(S)

    Event Queue(s) www.ti.com Figure 2-13. Error Interrupt Operation EMR/EMRH QEMR CCERR EEVAL.EVAL Eval/ pulse EDMA3CC_ERRINT 2.10 Event Queue(s) Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC. Each queue is 16 entries deep, that is, a maximum of 16 queued events per event queue.

  • Page 56: Dma/Qdma Channel To Event Queue Mapping

    Event Queue(s) www.ti.com 2.10.1 DMA/QDMA Channel to Event Queue Mapping Each of the 64 DMA channels and 8 QDMA channels are independently programmed to map to a specific queue using the DMA queue number register (DMAQNUM) and the QDMA queue number register (QDMANUM).

  • Page 57: Edma3 Transfer Controller (Edma3Tc)

    EDMA3 Transfer Controller (EDMA3TC) www.ti.com 2.11 EDMA3 Transfer Controller (EDMA3TC) The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller (EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR) to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR;...

  • Page 58: Error Generation

    EDMA3 Transfer Controller (EDMA3TC) www.ti.com Table 2-15. Read/Write Command Optimization Rules SAM/DAM = ACNT ≤ DBS BCNT ≤ 1023 ACNT is power of 2 BIDX = ACNT Increment Description Optimized Not Optimized Not Optimized Not Optimized Not Optimized Not Optimized 2.11.1.2 TR Pipelining TR pipelining refers to the ability of the source active set to get ahead of the destination active set.

  • Page 59: Debug Features

    EDMA3 Transfer Controller (EDMA3TC) www.ti.com 2.11.3 Debug Features The DMA program register set, DMA source active register set, and the destination FIFO register set are used to derive a brief history of TRs serviced through the transfer controller. Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing activity within different parts of the transfer controller: •...

  • Page 60: Event Dataflow

    Event Dataflow www.ti.com 2.12 Event Dataflow This section summarizes the data flow of a single event, from the time the event is latched to the channel controller to the time the transfer completion code is returned. The following steps list the sequence of EDMA3CC activity: 1.

  • Page 61: Edma3 Prioritization

    EDMA3 Prioritization www.ti.com 2.13 EDMA3 Prioritization The EDMA3 controller has many implementation rules to deal with concurrent events/channels, transfers, etc. The following subsections detail various arbitration details whenever there might be occurrence of concurrent activity. Figure 2-14 shows the different places EDMA3 priorities come into play. 2.13.1 Channel Priority The DMA event registers (ER and ERH) capture up to 64 events;...

  • Page 62: Trigger Source Priority

    EDMA3 Operating Frequency (Clock Control) www.ti.com 2.13.2 Trigger Source Priority If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain trigger), and if multiple events are set simultaneously for the same channel (ER.En = 1, ESR.En = 1, CER.En = 1), then the EDMA3CC always services these events in the following priority order: event trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than manual trigger (via ESR).

  • Page 63: Power Management

    For detailed information on power management procedures using the PSC, see the TMS320DM357 DMSoC ARM Subsystem Reference Guide (SPRUG25). The EDMA3 controller can be idled on receiving a clock stop request from the PSC. The requests to EDMA3CC and EDMA3TC are separate.
  • Page 64 EDMA3 Architecture SPRUG34 – November 2008 Submit Documentation Feedback...

  • Page 65: Edma3 Transfer Examples

    Chapter 3 SPRUG34 – November 2008 EDMA3 Transfer Examples The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration. The following sections provides a description and PaRAM configuration for some typical use case scenarios....................Topic Page ..............

  • Page 66: Block Move Example

    Block Move Example www.ti.com Block Move Example The most basic transfer performed by the EDMA3 is a block move. During device operation it is often necessary to transfer a block of data from one location to another, usually between on-chip and off-chip memory.

  • Page 67: Block Move Example Param Configuration

    Block Move Example www.ti.com Figure 3-2. Block Move Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0010 0008h Channel Options Parameter (OPT) 8000 0000h Channel Source Address (SRC) 0001h 0100h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0000h...

  • Page 68: Subframe Extraction Example

    Subframe Extraction Example www.ti.com Subframe Extraction Example The EDMA3 can efficiently extract a small frame of data from a larger frame of data. By performing a 2D-to-1D transfer, the EDMA3 retrieves a portion of data for the CPU to process. In this example, a 640 ×...

  • Page 69: Subframe Extraction Example Param Configuration

    Subframe Extraction Example www.ti.com Figure 3-4. Subframe Extraction Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0010 000Ch Channel Options Parameter (OPT) 8000 0788h Channel Source Address (SRC) 000Ch 0020h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0020h...

  • Page 70: Data Sorting Example

    Data Sorting Example www.ti.com Data Sorting Example Many applications require the use of multiple data arrays; it is often desirable to have the arrays arranged such that the first elements of each array are adjacent, the second elements are adjacent, and so on. Often this is not how the data is presented to the device.

  • Page 71: Data Sorting Example Param Configuration

    Data Sorting Example www.ti.com Figure 3-6. Data Sorting Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0090 0004h Channel Options Parameter (OPT) 8000 0000h Channel Source Address (SRC) 0400h 0004h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0010h...

  • Page 72: Peripheral Servicing Example

    Peripheral Servicing Example www.ti.com Peripheral Servicing Example The EDMA3 channel controller also services peripherals in the background of CPU operation, without requiring any CPU intervention. Through proper initialization of the DMA channels, they can be configured to continuously service on-chip and off-chip peripherals throughout the device operation. Each event available to the EDMA3 has its own dedicated channel, and all channels operate simultaneously.

  • Page 73: Servicing Incoming Asp Data Example Param

    Peripheral Servicing Example www.ti.com Figure 3-8. Servicing Incoming ASP Data Example PaRAM (a) EDMA Parameters Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0100h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h...

  • Page 74: Bursting Peripherals

    Peripheral Servicing Example www.ti.com 3.4.2 Bursting Peripherals Higher bandwidth applications require that multiple data elements be presented to the CPU for every synchronization event. This frame of data can either be from multiple sources that are working simultaneously or from a single high-throughput peripheral that streams data to/from the CPU. In this example, a port is receiving a video frame from a camera and presenting it to the CPU one array at a time.

  • Page 75: Servicing Peripheral Burst Example Param

    Peripheral Servicing Example www.ti.com Figure 3-10. Servicing Peripheral Burst Example PaRAM (a) EDMA Parameters Parameter Contents Parameter 0010 0004h Channel Options Parameter (OPT) Channel Source Address Channel Source Address (SRC) 0280h 0002h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 8000 0000h Channel Destination Address (DST) 0002h...

  • Page 76: Continuous Operation

    Peripheral Servicing Example www.ti.com 3.4.3 Continuous Operation Configuring a DMA channel to receive a single frame of data is useful, and is applicable to some systems. A majority of the time, however, data is going to be continuously transmitted and received throughout the entire operation of the CPU.

  • Page 77: Servicing Continuous Asp Data Example Param

    Peripheral Servicing Example www.ti.com Figure 3-12. Servicing Continuous ASP Data Example PaRAM (a) EDMA Parameters for Receive Channel (PaRAM Set 3) being Linked to PaRAM Set 64 Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT)

  • Page 78: Servicing Continuous Asp Data Example Reload Param

    Peripheral Servicing Example www.ti.com Figure 3-13. Servicing Continuous ASP Data Example Reload PaRAM (a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h...

  • Page 79: Ping-Pong Buffering

    Peripheral Servicing Example www.ti.com 3.4.4 Ping-Pong Buffering Although the previous configuration allows the EDMA3 to service a peripheral continuously, it presents a number of restrictions to the CPU. Since the input and output buffers are continuously being filled/emptied, the CPU must match the pace of the EDMA3 very closely in order to process the data. The EDMA3 receive data must always be placed in memory before the CPU accesses it, and the CPU must provide the output data before the EDMA3 transfers it.

  • Page 80: Ping-Pong Buffering For Asp Data Example

    Peripheral Servicing Example www.ti.com Figure 3-14. Ping-Pong Buffering for ASP Data Example ..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1 Ping Pong 1180 0000h 1180 0800h A10i A11i A12i A13i A10i A11i A12i A13i 01E0 2000h 1180 0080h 1180 0880h REVT B10i B11i B12i B13i B10i B11i B12i B13i 1180 1000h XEVT 1180 1800h...

  • Page 81: Ping-Pong Buffering For Asp Example Pong Param

    Peripheral Servicing Example www.ti.com (c) EDMA Parameters for Channel 2 (Using PaRAM Set 2 Linked to Pong Set 65) Parameter Contents Parameter 0010 2000h Channel Options Parameter (OPT) 1180 1000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST)

  • Page 82: Transfer Chaining Examples

    Peripheral Servicing Example www.ti.com Figure 3-17. Ping-Pong Buffering for ASP Example Ping PaRAM (a) EDMA Ping Parameters for Channel 3 at Set 65 Linked to Set 64 Parameter Contents Parameter 0010 D000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT)

  • Page 83: Intermediate Transfer Completion Chaining Example

    Peripheral Servicing Example www.ti.com Figure 3-18. Intermediate Transfer Completion Chaining Example Hardwired event Chained event (tied to GPINT0, event 32) (event 63) Event 32 Intermediate transfer complete Channel 32, array 0 Channel 63, array 0 Event 32 Intermediate transfer complete Channel 32, array 1 Channel 63, array 1 Event 32...

  • Page 84: Single Large Block Transfer Example

    Peripheral Servicing Example www.ti.com Figure 3-19. Single Large Block Transfer Example Event 25 (CPU writes 1 to ESR.E25) EDMA3 channel 25 setup ACNT = 16384 16 KBytes data transfer BCNT = 1 CCNT = 1 1D transfer of 16 KByte elements OPT.ITCINTEN = 0 OPT.TCC = Don’t care The intermediate transfer chaining enable (ITCCHEN) provides a method to break up a large transfer into...

  • Page 85: Registers

    Chapter 4 SPRUG34 – November 2008 Registers This chapter discusses the registers of the EDMA3 controller....................Topic Page .............. Register Memory Maps ..........Parameter RAM (PaRAM) Entries ....... EDMA3 Channel Controller Control Registers ......EDMA3 Transfer Controller Control Registers SPRUG34 –...

  • Page 86: Register Memory Maps

    Register Memory Maps www.ti.com Register Memory Maps See your device-specific data manual for the register memory maps. Parameter RAM (PaRAM) Entries Table 4-1 lists the parameter RAM (PaRAM) entries for the EDMA3 channel controller (EDMA3CC). See the device-specific data manual for the memory address of these registers. Table 4-1.

  • Page 87: Channel Options Parameter (Opt)

    Parameter RAM (PaRAM) Entries www.ti.com 4.2.1 Channel Options Parameter (OPT) The channel options parameter (OPT) is shown in Figure 4-1 and described in Table 4-2. Figure 4-1. Channel Options Parameter (OPT) Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...
  • Page 88 Parameter RAM (PaRAM) Entries www.ti.com Table 4-2. Channel Options Parameters (OPT) Field Descriptions (continued) Field Value Description TCCMODE Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. Normal completion: A transfer is considered completed after the data has been transferred. Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC.

  • Page 89: Channel Source Address Parameter (Src)

    Parameter RAM (PaRAM) Entries www.ti.com 4.2.2 Channel Source Address Parameter (SRC) The channel source address parameter (SRC) specifies the starting byte address of the source. The SRC is shown in Figure 4-2 and described in Table 4-3. Figure 4-2. Channel Source Address Parameter (SRC) R/W-x R/W-x LEGEND: R/W = Read/Write;...

  • Page 90: Channel Destination Address Parameter (Dst)

    Parameter RAM (PaRAM) Entries www.ti.com 4.2.4 Channel Destination Address Parameter (DST) The channel destination address parameter (DST) specifies the starting byte address of the source. The DST is shown in Figure 4-4 and described in Table 4-5. Figure 4-4. Channel Destination Address Parameter (DST) R/W-x R/W-x LEGEND: R/W = Read/Write;...

  • Page 91: Link Address/B Count Reload Parameter (Link_Bcntrld)

    Parameter RAM (PaRAM) Entries www.ti.com 4.2.6 Link Address/B Count Reload Parameter (LINK_BCNTRLD) The link address/B count reload parameter (LINK_BCNTRLD) specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads the next PaRAM set during linking and the value used to reload the BCNT field in the A count/B count parameter (A_B_CNT) once the last array in the 2nd dimension is transferred.

  • Page 92: Source C Index/Destination C Index Parameter (Src_Dst_Cidx)

    Parameter RAM (PaRAM) Entries www.ti.com 4.2.7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) The source C index/destination C index parameter (SRC_DST_CIDX) specifies the value (2s complement) used for source address modification between each array in the 3rd dimension and the value (2s complement) used for destination address modification between each array in the 3rd dimension.

  • Page 93: Edma3 Channel Controller Control Registers

    EDMA3 Channel Controller Control Registers www.ti.com EDMA3 Channel Controller Control Registers Table 4-10 lists the memory-mapped registers for the EDMA3 channel controller (EDMACC). See the device-specific data manual for the memory address of these registers and for the shadow region addresses.
  • Page 94 EDMA3 Channel Controller Control Registers www.ti.com Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 038Ch QRAE3 QDMA Region Access Enable Register for Region 3 Section 4.3.3.2 0400h-047Ch Q0E0-Q1E15 Event Queue Entry Registers Q0E0-Q1E15 Section 4.3.4.1 0600h QSTAT0 Queue 0 Status Register Section 4.3.4.2 0604h QSTAT1...
  • Page 95 EDMA3 Channel Controller Control Registers www.ti.com Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 200Ch ECRH Event Clear Register High 2010h Event Set Register 2014h ESRH Event Set Register High 2018h Chained Event Register 201Ch CERH Chained Event Register High 2020h Event Enable Register 2024h...
  • Page 96 EDMA3 Channel Controller Control Registers www.ti.com Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 2234h EESRH Event Enable Set Register High 2238h Secondary Event Register 223Ch SERH Secondary Event Register High 2240h SECR Secondary Event Clear Register 2244h SECRH Secondary Event Clear Register High 2250h...

  • Page 97: Global Registers

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.1 Global Registers 4.3.1.1 Peripheral Identification Register (PID) The peripheral identification register (PID) uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC. The PID is shown in Figure 4-9 and described in Table 4-11.

  • Page 98: Edma3Cc Configuration Register (Cccfg) Field Descriptions

    EDMA3 Channel Controller Control Registers www.ti.com Table 4-12. EDMA3CC Configuration Register (CCCFG) Field Descriptions Field Value Description 31-26 Reserved 0-3Fh Reserved MP_EXIST Memory protection existence. No memory protection. Reserved CHMAP_EXIST Channel mapping existence No channel mapping. This implies that there is fixed association for a channel number to a parameter entry number or, in other words, PaRAM entry n corresponds to channel n.

  • Page 99: Qdma Channel Map N Registers (Qchmapn)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.1.3 QDMA Channel Map n Registers (QCHMAPn) Each QDMA channel in EDMA3CC can be associated with any PaRAM set available on the device. Furthermore, the specific trigger word (0-7) of the PaRAM set can be programmed. The PaRAM set association and trigger word for every QDMA channel register is configurable using the QDMA channel map n register (QCHMAPn).

  • Page 100: Dma Channel Queue Number Registers (Dmaqnumn)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.1.4 DMA Channel Queue Number Registers (DMAQNUMn) The DMA channel queue number register (DMAQNUMn) allows programmability of each of the 64 DMA channels in the EDMA3CC to submit its associated synchronization event to any event queue in the EDMA3CC.

  • Page 101: Qdma Channel Queue Number Register (Qdmaqnum)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.1.5 QDMA Channel Queue Number Register (QDMAQNUM) The QDMA channel queue number register (QDMAQNUM) is used to program all the QDMA channels in the EDMA3CC to submit the associated QDMA event to any of the event queues in the EDMA3CC. The QDMAQNUM is shown in Figure 4-13 and described in...

  • Page 102: Error Registers

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.1.6 Queue Priority Register (QUEPRI) The queue priority register (QUEPRI) allows you to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue. Since the queue to EDMA3TC mapping is fixed, programming QUEPRI essentially governs the priority of the associated transfer controller(s) read/write commands with respect to the other bus masters in the device.

  • Page 103: Event Missed Register (Emr)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-15. Event Missed Register (EMR) LEGEND: R = Read only; -n = value after reset Table 4-18. Event Missed Register (EMR) Field Descriptions Field Value Description 31-0 Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear register (EMCR).

  • Page 104: Event Missed Clear Register (Emcr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.2 Event Missed Clear Registers (EMCR/EMCRH) Once a missed event is posted in the event missed registers (EMR/EMRH), the bit remains set and you need to clear the set bit(s). This is done by way of CPU writes to the event missed clear registers (EMCR/EMCRH).

  • Page 105: Qdma Event Missed Register (Qemr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.3 QDMA Event Missed Register (QEMR) For a particular QDMA channel, if two QDMA events are detected without the first event getting cleared/serviced, the bit corresponding to that channel is set/asserted in the QDMA event missed register (QEMR).

  • Page 106: Qdma Event Missed Clear Register (Qemcr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.4 QDMA Event Missed Clear Register (QEMCR) Once a missed event is posted in the QDMA event missed registers (QEMR), the bit remains set and you need to clear the set bit(s). This is done by way of CPU writes to the QDMA event missed clear registers (QEMCR).

  • Page 107: Edma3Cc Error Register (Ccerr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.5 EDMA3CC Error Register (CCERR) The EDMA3CC error register (CCERR) indicates whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).

  • Page 108: Edma3Cc Error Clear Register (Ccerrclr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.6 EDMA3CC Error Clear Register (CCERRCLR) The EDMA3CC error clear register (CCERRCLR) is used to clear any error bits that are set in the EDMA3CC error register (CCERR). In addition, CCERRCLR also clears the values of some bit fields in the queue status registers (QSTATn) associated with a particular event queue.

  • Page 109: Error Evaluation Register (Eeval)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.2.7 Error Evaluation Register (EEVAL) The EDMA3CC error interrupt is asserted whenever an error bit is set in any of the error registers (EMR/EMRH, QEMR, and CCERR). For subsequent error bits that get set, the EDMA3CC error interrupt is reasserted only when transitioning from an “all the error bits cleared”...

  • Page 110: Region Access Enable Registers

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.3 Region Access Enable Registers The region access enable register group consists of the DMA access enable registers (DRAEm and DRAEHm) and the QDMA access enable registers (QRAEm). Where m is the number of shadow regions in the EDMA3CC memory map for a device.

  • Page 111: Qdma Region Access Enable For Region M (Qraem)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.3.2 QDMA Region Access Enable Registers (QRAEm) The QDMA region access enable register for shadow region m (QRAEm) is programmed to allow or disallow read/write accesses on a bit-by-bit bases for all QDMA registers in the shadow region m view of the QDMA registers.

  • Page 112: Status/Debug Visibility Registers

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.4 Status/Debug Visibility Registers The following set of registers provide visibility into the event queues and a TR lifecycle. These are useful for system debug as they provide in-depth visibility for the events queued up in the event queue and also provide information on what parts of the EDMA3CC logic are active once the event has been received by the EDMA3CC.

  • Page 113: Queue N Status Register (Qstatn)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.4.2 Queue n Status Registers (QSTATn) The queue n status register (QSTATn) is shown in Figure 4-28 and described in Table 4-30. Figure 4-28. Queue n Status Register (QSTATn) Reserved THRXCD Reserved Reserved NUMVAL Reserved STRTPTR LEGEND: R = Read only;...

  • Page 114: Queue Watermark Threshold A Register (Qwmthra)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.4.3 Queue Watermark Threshold A Register (QWMTHRA) The queue watermark threshold A register (QWMTHRA) is shown in Figure 4-29 and described in Table 4-31. Figure 4-29. Queue Watermark Threshold A Register (QWMTHRA) Reserved Reserved Reserved R/W-10h R/W-10h...

  • Page 115: Edma3Cc Status Register (Ccstat)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.4.4 EDMA3CC Status Register (CCSTAT) The EDMA3CC status register (CCSTAT) has a number of status bits that reflect which parts of the EDMA3CC logic is active at any given instant of time. The CCSTAT is shown in Figure 4-30 described in Table...

  • Page 116: Dma Channel Registers

    EDMA3 Channel Controller Control Registers www.ti.com Table 4-32. EDMA3CC Status Register (CCSTAT) Field Descriptions (continued) Field Value Description WSTATACTV Write status interface active. Write status req is idle and write status fifo is idle. Either the write status request is active or additional write status responses are pending in the write status fifo.

  • Page 117: Event Register (Er)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-31. Event Register (ER) LEGEND: R = Read only; -n = value after reset Table 4-33. Event Register (ER) Field Descriptions Field Value Description 31-0 Event 0-31. Events 0-31 are captured by the EDMA3CC and are latched into ER. The events are set (En = 1) even when events are disabled (En = 0 in the event enable register, EER).

  • Page 118: Event Clear Register (Ecr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.5.2 Event Clear Registers (ECR, ECRH) Once an event has been posted in the event registers (ER/ERH), the event is cleared in two ways. If the event is enabled in the event enable register (EER/EERH) and the EDMA3CC submits a transfer request for the event to the EDMA3TC, it clears the corresponding event bit in the event register.

  • Page 119: Event Set Register (Esr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.5.3 Event Set Registers (ESR, ESRH) The event set registers (ESR/ESRH) allow the CPU (or EDMA programmers) to manually set events to initiate DMA transfer requests. CPU writes of 1 to any event set register (En) bits set the corresponding bits in the registers.

  • Page 120: Event Set Register High (Esrh)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-36. Event Set Register High (ESRH) RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0...

  • Page 121: Chained Event Register (Cer)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-37. Chained Event Register (CER) LEGEND: R = Read only; -n = value after reset Table 4-39. Chained Event Register (CER) Field Descriptions Field Value Description 31-0 Chained event for event 0-31. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC.

  • Page 122: Event Enable Register (Eer)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.5.5 Event Enable Registers (EER, EERH) The EDMA3CC provides the option of selectively enabling/disabling each event in the event registers (ER/ERH) by using the event enable registers (EER/EERH). If an event bit in EER/EERH is set to 1 (using the event enable set registers, EESR/EESRH), it will enable that corresponding event.

  • Page 123: Event Enable Clear Register (Eecr)

    EDMA3 Channel Controller Control Registers www.ti.com Table 4-42. Event Enable Register High (EERH) Field Descriptions Field Value Description 31-0 Event enable for events 32-63. Event is not enabled. An external event latched in the event register high (ERH) is not evaluated by the EDMA3CC.

  • Page 124: Event Enable Set Register (Eesr)

    EDMA3 Channel Controller Control Registers www.ti.com Table 4-44. Event Enable Clear Register High (EECRH) Field Descriptions Field Value Description 31-0 Event enable clear for events 32-63. No effect. Event is disabled. Corresponding bit in the event enable register high (EERH) is cleared (En = 0). 4.3.5.7 Event Enable Set Registers (EESR, EESRH) The event enable registers (EER/EERH) cannot be modified by directly writing to them.

  • Page 125: Secondary Event Register (Ser)

    EDMA3 Channel Controller Control Registers www.ti.com Table 4-46. Event Enable Set Register High (EESRH) Field Descriptions Field Value Description 31-0 Event enable set for events 32-63. No effect. Event is enabled. Corresponding bit in the event enable register high (EERH) is set (En = 1). 4.3.5.8 Secondary Event Registers (SER, SERH) The secondary event registers (SER/SERH) provide information on the state of a DMA channel or event...

  • Page 126: Secondary Event Register High (Serh)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-46. Secondary Event Register High (SERH) LEGEND: R = Read only; -n = value after reset Table 4-48. Secondary Event Register High (SERH) Field Descriptions Field Value Description 31-0 Secondary event register. The secondary event register is used to provide information on the state of an event.

  • Page 127: Secondary Event Clear Register High (Secrh)

    EDMA3 Channel Controller Control Registers www.ti.com Figure 4-48. Secondary Event Clear Register High (SECRH) LEGEND: W = Write only; -n = value after reset Table 4-50. Secondary Event Clear Register High (SECRH) Field Descriptions Field Value Description 31-0 Secondary event clear register. No effect.

  • Page 128: Interrupt Registers

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6 Interrupt Registers All DMA/QDMA channels can be set to assert an EDMA3CC completion interrupt to the CPU on transfer completion, by appropriately configuring the PaRAM entry associated with the channels. The following set of registers is used for the transfer completion interrupt reporting/generating by the EDMA3CC.

  • Page 129: Interrupt Enable Clear Register (Iecr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6.2 Interrupt Enable Clear Register (IECR, IECRH) The interrupt enable clear registers (IECR/IECRH) are used to clear interrupts. Writes of 1 to the bits in IECR/IECRH clear the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0 have no effect.

  • Page 130: Interrupt Enable Set Register (Iesr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6.3 Interrupt Enable Set Registers (IESR, IESRH) The interrupt enable set registers (IESR/IESRH) are used to enable interrupts. Writes of 1 to the bits in IESR/IESRH set the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0 have no effect.

  • Page 131: Interrupt Pending Register (Ipr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6.4 Interrupt Pending Register (IPR, IPRH) If the TCINTEN and/or ITCINTEN bit in the channel option parameter (OPT) is set to 1 in the PaRAM entry associated with the channel (DMA or QDMA), then the EDMA3TC (for normal completion) or the EDMA3CC (for early completion) returns a completion code on transfer or intermediate transfer completion.

  • Page 132: Interrupt Clear Register (Icr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6.5 Interrupt Clear Registers (ICR, ICRH) The bits in the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bits in the interrupt clear registers(ICR/ICRH). Writes of 0 have no effect. All set bits in IPR/IPRH must be cleared to allow EDMA3CC to assert additional transfer completion interrupts.

  • Page 133: Interrupt Evaluate Register (Ieval)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.6.6 Interrupt Evaluate Register (IEVAL) The interrupt evaluate register (IEVAL) is the only register that physically exists in both the global region and the shadow regions. In other words, the read/write accessibility for the shadow region IEVAL is not affected by the DMA/QDMA region access registers (DRAEm/DRAEHm, QRAEn/QRAEHn).

  • Page 134: Qdma Event Register (Qer)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7 QDMA Registers The following sets of registers control the QDMA channels in the EDMA3CC. The QDMA channels (with the exception of the QDMA queue number register) consist of a set of registers, each of which have a bit location.

  • Page 135: Qdma Event Enable Register (Qeer)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7.2 QDMA Event Enable Register (QEER) The EDMA3CC provides the option of selectively enabling/disabling each channel in the QDMA event register (QER) by using the QDMA event enable register (QEER). If any of the event bits in QEER is set to 1 (using the QDMA event enable set register, QEESR), it will enable that corresponding event.

  • Page 136: Qdma Event Enable Clear Register (Qeecr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7.3 QDMA Event Enable Clear Register (QEECR) The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to ease the software burden when multiple tasks are attempting to simultaneously modify these registers. The QDMA event enable clear register (QEECR) is used to disable events.

  • Page 137: Qdma Event Enable Set Register (Qeesr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7.4 QDMA Event Enable Set Register (QEESR) The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to ease the software burden when multiple tasks are attempting to simultaneously modify these registers. The QDMA event enable set register (QEESR) is used to enable events.

  • Page 138: Qdma Secondary Event Register (Qser)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7.5 QDMA Secondary Event Register (QSER) The QDMA secondary event register (QSER) provides information on the state of a QDMA event. If at any time a bit corresponding to a QDMA channel is set in QSER, that implies that the corresponding QDMA event is in the queue.

  • Page 139: Qdma Secondary Event Clear Register (Qsecr)

    EDMA3 Channel Controller Control Registers www.ti.com 4.3.7.6 QDMA Secondary Event Clear Register (QSECR) The QDMA secondary event clear register (QSECR) clears the status of the QDMA secondary event register (QSER) and the QDMA event register (QER). CPU writes of 1 clear the corresponding set bits in QSER and QER.

  • Page 140: Edma3 Transfer Controller Registers

    EDMA3 Transfer Controller Control Registers www.ti.com EDMA3 Transfer Controller Control Registers Table 4-68 lists the memory-mapped registers for the EDMA3 transfer controller (EDMA3TC). See the device-specific data manual for the memory address of these registers. All other register offset addresses not listed in Table 4-68 should be considered as reserved locations and the register contents should not...

  • Page 141: Peripheral Id Register (Pid)

    EDMA3 Transfer Controller Control Registers www.ti.com Table 4-68. EDMA3 Transfer Controller Registers (continued) Offset Acronym Register Description Section 03C8h DFCNT3 Destination FIFO Count Register 3 Section 4.4.6.12 03CCh DFDST3 Destination FIFO Destination Address Register 3 Section 4.4.6.13 03D0h DFBIDX3 Destination FIFO BIDX Register 3 Section 4.4.6.14 03D4h DFMPPRXY3...

  • Page 142: Edma3Tc Configuration Register (Tccfg)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.2 EDMA3TC Configuration Register (TCCFG) The EDMA3TC configuration register (TCCFG) is shown in Figure 4-67 and described in Table 4-70. Figure 4-67. EDMA3TC Configuration Register (TCCFG) Reserved Reserved DREGDEPTH Reserved BUSWIDTH Rsvd FIFOSIZE LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset Table 4-70.

  • Page 143: Edma3Tc Channel Status Register (Tcstat)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.3 EDMA3TC Channel Status Register (TCSTAT) The EDMA3TC channel status register (TCSTAT) is shown in Figure 4-68 and described in Table 4-71. Figure 4-68. EDMA3TC Channel Status Register (TCSTAT) Reserved Reserved DFSTRTPTR Reserved Reserved Reserved DSTACTV Reserved...

  • Page 144: Error Status Register (Errstat)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.4 Error Registers 4.4.4.1 Error Status Register (ERRSTAT) The error status register (ERRSTAT) is shown in Figure 4-69 and described in Table 4-72. Figure 4-69. Error Status Register (ERRSTAT) Reserved Reserved MMRAERR TRERR Reserved BUSERR LEGEND: R = Read only;...

  • Page 145: Error Enable Register (Erren)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.4.2 Error Enable Register (ERREN) The error enable register (ERREN) is shown in Figure 4-70 and described in Table 4-73. When any of the enable bits in ERREN is set, a bit set in the corresponding error status register (ERRSTAT) causes an assertion of the EDMA3TC interrupt.

  • Page 146: Error Clear Register (Errclr)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.4.3 Error Clear Register (ERRCLR) The error clear register (ERRCLR) is shown in Figure 4-71 and described in Table 4-74. Figure 4-71. Error Clear Register (ERRCLR) Reserved Reserved MMRAERR TRERR Reserved BUSERR LEGEND: R = Read only; W = Write only; -n = value after reset Table 4-74.

  • Page 147: Error Details Register (Errdet)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.4.4 Error Details Register (ERRDET) The error details register (ERRDET) is shown in Figure 4-72 and described in Table 4-75. Figure 4-72. Error Details Register (ERRDET) Reserved TCCHEN TCINTEN Reserved Reserved STAT LEGEND: R = Read only; -n = value after reset Table 4-75.

  • Page 148: Error Interrupt Command Register (Errcmd)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.4.5 Error Interrupt Command Register (ERRCMD) The error command register (ERRCMD) is shown in Figure 4-73 and described in Table 4-76. Figure 4-73. Error Interrupt Command Register (ERRCMD) Reserved Reserved Rsvd EVAL LEGEND: R = Read only; W = Write only; -n = value after reset Table 4-76.

  • Page 149: Read Rate Register (Rdrate)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.5 Read Rate Register (RDRATE) The EDMA3 transfer controller issues read commands at a rate controlled by the read rate register (RDRATE). The RDRATE defines the number of idle cycles that the read controller must wait before issuing subsequent commands.

  • Page 150: Source Active Options Register (Saopt)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.1 Source Active Options Register (SAOPT) The source active options register (SAOPT) is shown in Figure 4-75 and described in Table 4-78. Figure 4-75. Source Active Options Register (SAOPT) Reserved TCCHEN Rsvd TCINTEN Reserved R/W-0 R/W-0 R/W-0...

  • Page 151: Source Active Source Address Register (Sasrc)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.2 Source Active Source Address Register (SASRC) The source active source address register (SASRC) is shown in Figure 4-76 and described in Table 4-79. Figure 4-76. Source Active Source Address Register (SASRC) SADDR SADDR LEGEND: R = Read only;...

  • Page 152: Source Active Destination Address Register (Sadst)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.4 Source Active Destination Address Register (SADST) The source active destination address register (SADST) is shown in Figure 4-78 and described in Table 4-81. Figure 4-78. Source Active Destination Address Register (SADST) DADDR DADDR LEGEND: R = Read only;...

  • Page 153: Source Active Memory Protection Proxy Register (Sampprxy)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.6 Source Active Memory Protection Proxy Register (SAMPPRXY) The source active memory protection proxy register (SAMPPRXY) is shown in Figure 4-80 and described Table 4-83. Figure 4-80. Source Active Memory Protection Proxy Register (SAMPPRXY) Reserved Reserved PRIV...

  • Page 154: Source Active Count Reload Register (Sacntrld)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.7 Source Active Count Reload Register (SACNTRLD) The source active count reload register (SACNTRLD) is shown in Figure 4-81 and described in Table 4-84. Figure 4-81. Source Active Count Reload Register (SACNTRLD) Reserved ACNTRLD LEGEND: R/W = Read/Write;...

  • Page 155: Source Active Destination Address B-Reference Register (Sadstbref)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.9 Source Active Destination Address B-Reference Register (SADSTBREF) The source active destination address B-reference register (SADSTBREF) is shown in Figure 4-83 described in Table 4-86. Figure 4-83. Source Active Destination Address B-Reference Register (SADSTBREF) DADDRBREF DADDRBREF LEGEND: R = Read only;...

  • Page 156: Destination Fifo Options Register (Dfoptn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.10 Destination FIFO Options Register (DFOPTn) The destination FIFO options register (DFOPTn) is shown in Figure 4-84 and described in Table 4-87. Note: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC. Figure 4-84.

  • Page 157: Destination Fifo Source Address Register (Dfsrcn)

    EDMA3 Transfer Controller Control Registers www.ti.com Table 4-87. Destination FIFO Options Register (DFOPTn) Field Descriptions (continued) Field Value Description Source address mode within an array. Increment (INCR) mode. Source addressing within an array increments. Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width.

  • Page 158: Destination Fifo Count Register (Dfcntn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.12 Destination FIFO Count Register (DFCNTn) The destination FIFO count register (DFCNTn) is shown in Figure 4-86 and described in Table 4-89. Note: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC. Figure 4-86.

  • Page 159: Destination Fifo Destination Address Register (Dfdstn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.13 Destination FIFO Destination Address Register (DFDSTn) The destination FIFO destination address register (DFDSTn) is shown in Figure 4-87 and described in Table 4-90. Note: The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC. Figure 4-87.

  • Page 160: Destination Fifo Memory Protection Proxy Register (Dfmpprxyn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.15 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) The destination FIFO memory protection proxy register (DFMPPRXYn) is shown in Figure 4-89 described in Table 4-92. Figure 4-89. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Reserved Reserved PRIV...

  • Page 161: Destination Fifo Count Reload Register (Dfcntrldn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.16 Destination FIFO Count Reload Register (DFCNTRLDn) The destination FIFO count reload register (DFCNTRLDn) is shown in Figure 4-90 and described in Table 4-93. Figure 4-90. Destination FIFO Count Reload Register (DFCNTRLDn) Reserved ACNTRLD LEGEND: R = Read only;...

  • Page 162: Destination Fifo Destination Address B-Reference Register (Dfdstbrefn)

    EDMA3 Transfer Controller Control Registers www.ti.com 4.4.6.18 Destination FIFO Destination Address B-Reference (DFDSTBREFn) The destination FIFO destination address B-reference register (DFDSTBREFn) is shown in Figure 4-92 and described in Table 4-95. Figure 4-92. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) DADDRBREF DADDRBREF LEGEND: R = Read only;...

  • Page 163: Sprug34 - November 2008

    Appendix A SPRUG34 – November 2008 Tips Debug Checklist This section lists some tips to keep in mind while debugging applications using the EDMA3. Table A-1 provides some common issues and their probable causes and resolutions. Table A-1. Debug List Issue Description/Solution The transfer associated with the channel...
  • Page 164 Miscellaneous Programming/Debug Tips www.ti.com Table A-1. Debug List (continued) Issue Description/Solution Completion interrupts are not asserted, or You must ensure the following: no further interrupts are received after the 1. The interrupt generation is enabled in the OPT of the associated PaRAM set first completion interrupt.
  • Page 165 Appendix B SPRUG34 – November 2008 Setting Up a Transfer The following list provides a quick guide for the typical steps involved in setting up a transfer. 1. Initiating a DMA/QDMA channel: a. Determine the type of channel (QDMA or DMA) to be used. b.
  • Page 166 Appendix B www.ti.com 5. Wait for completion: a. If the interrupts are enabled as mentioned in step 3, then the EDMA3CC generates a completion interrupt to the CPU whenever transfer completion results in setting the corresponding bits in the interrupt pending register (IPR/IPRH). The set bits must be cleared in IPR\IPRH by writing to the corresponding bit in ICR\ICRH.
  • Page 167 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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