Dspf_Sp_Dotp_Cplx - Texas Instruments TMS320C67 DSP Series Programmer's Reference Manual

DSPF_sp_dotp_cplx

Implementation Notes
Benchmarks
DSPF_sp_dotp_cplx
Function
Arguments
4-54
-
LDDW instructions are used to load two SP floating-point values at a time
for the x and y arrays.
-
The loop is unrolled once and software pipelined. However, by condition-
ally adding to the dot product odd numbered array sizes are also per-
mitted.
-
Since the ADDSP and MPYSP instructions take 4 cycles, A8, B8, A0, and
B0 multiplex different variables to save on register usage. This multiple as-
signment is possible since the variables are always read just once on the
first cycle that they are available.
-
The loop is primed to reduce the prolog by 4 cycles (14 words) with no in-
crease in cycle time.
-
The load counter is used as the loop counter which requires a 3-cycle
(6 word) epilog to finish the calculations. This does not increase the cycle
time.
-
Endianess: This code is little endian.
-
Interruptibility: This code is interrupt-tolerant but not interruptible.
Cycles nx/2 + 25
e.g., for nx = 512, cycles = 281
Code size 256
(in bytes)
Complex single-precision floating-point dot product
void DSPF_sp_dotp_cplx (const float *x, const float *y, int n, float *restrict
re, float * restrict im)
x Pointer to array holding the first floating-point vector.
y Pointer to array holding the second floating-point vector.
n Number of values in the x and y vectors.
re Pointer to the location storing the real part of the result.
im Pointer to the location storing the imaginary part of the
result.