Dspf_Sp_Cfftr4_Dif - Texas Instruments TMS320C67 DSP Series Programmer's Reference Manual

Implementation Notes
Benchmarks

DSPF_sp_cfftr4_dif

Function
Arguments
Description
-
LDDW is used to load in one complex number at a time (both the real and
the imaginary parts).
-
There are 12 stores in 10 cycles but all of them are to locations already
loaded. No use of the write buffer is made.
If nx ≤ 4K one can use the char (8-bit) data type for the index variable. This
-
would require changing the LDH when loading index values in the assem-
bly routine to LDB. This would further reduce the size of the index table by
half its size.
-
Endianess: Little endian configuration used.
-
Interruptibility: This code is interrupt-tolerant, but not interruptible.
Cycles (5/2)nx + 26
e.g., nx = 256, cycles = 666
Code size 608
(in bytes)
Single-precision floating-point decimation in frequency radix-4 FFT
with complex input
void DSPF_sp_cfftr4_dif (float* x, float* w, short n)
x Pointer to an array holding the input and output floating-point
array which contains 'n' complex points.
w Pointer to an array holding the coefficient floating-point array
which contains 3*n/4 complex numbers.
n Number of complex points in x.
This routine implements the DIF (decimation in frequency) complex radix 4
FFT with digit-reversed output and normal order input. The number of points,
'n', must be a power of 4 {4, 16, 64, 256, 1024, ...}. This routine is an in-place
routine in the sense that the output is written over the input. It is not an in-place
routine in the sense that the input is in normal order and the output is in digit-re-
versed order.
There must be n complex points (2*n values), and 3*n/4 complex coefficients
(3*n/2 values).
DSPF_sp_cfftr4_dif
DSPLIB Reference 4-9