Dspf_Sp_Biquad - Texas Instruments TMS320C67 DSP Series Programmer's Reference Manual

DSPF_sp_biquad

Implementation Notes
Benchmarks
DSPF_sp_biquad
Function
Arguments
4-44
-
The number of outputs (nr) must be a multiple of 4 and greater than or
equal to 4.
-
The 'index' (offset to start reading input array) must be mutiple of 2 and
less than or equal to (2^(csize-1) - 6).
-
The coefficient array is assured to be in reverse order; i.e., h(nh-1) to h(0)
hold coefficients h0, h1, h2, etc.
-
LDDW instructions are used to load two SP floating-point values simulta-
neously for the x and h arrays.
-
The outer loop is unrolled 4 times.
-
The inner loop is unrolled 2 times.
-
The variables prod1, prod3, prod5 and prod7 share A9.
The variables prod0, prod2, prod4 and prod6 share B6.
The variables sum1, sum3, sum5 and sum7 share A7.
The variables sum0, sum2, sum4 and sum6 share B8.
This multiple assignment is possible since the variables are always read
just once on the first cycle that they are avaliable.
-
A load counter is used so that an epilog is not needed. No extraneous
loads are performed.
-
Endianess: This code is LITLLE ENDIAN.
-
Interruptibility: This code is interrupt-tolerant but not interruptible.
Cycles (2*nh + 10) nr/4 + 18
For nh = 30 & nr=100, cycles = 1768
Code size 512
(in bytes)
Single-precision 2nd order IIR (biquad) filter
void DSPF_sp_biquad (float *x, float *b, float *a, float *delay, float *r, int
nx)
x Pointer to input samples.
b Pointer to Nr coefs b0, b1, b2.