Download
Share
Print this page
Texas Instruments TMS320F2807 Series Manual
  1. Manuals
  2. Brands
  3. Texas Instruments Manuals
  4. Microcontrollers
  5. TMS320F2807 Series
  6. Manual

Texas Instruments TMS320F2807 Series Manual

Mcus silicon revisions c, b
Hide thumbs Also See for TMS320F2807 Series:

Advertisement

Quick Links

Download this manual
1
Introduction
This document describes the silicon updates to the functional specifications for the TMS320F2807x
microcontrollers (MCUs).
The updates are applicable to the following:
•
176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack, PTP Suffix
•
100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack, PZP Suffix
2
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28075). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PTP) and temperature range (for example, T).
SPRZ423H – October 2014 – Revised February 2020
Submit Documentation Feedback
Copyright © 2014–2020, Texas Instruments Incorporated
SPRZ423H – October 2014 – Revised February 2020
TMS320F2807x MCUs
Silicon Revisions C, B
TMS320F2807x MCUs Silicon Revisions C, B
Silicon Errata
1

Advertisement

loading
Need help?

Need help?

Do you have a question about the TMS320F2807 Series and is the answer not in the manual?

Questions and answers

Related Manuals for Texas Instruments TMS320F2807 Series

Summary of Contents for Texas Instruments TMS320F2807 Series

  • Page 1 [TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMS320F28075). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).

  • Page 2: Device Markings

    100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) TECHNOLOGY F = Flash DEVICE 28076 28075 Figure 2. Example of Device Nomenclature TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 3 ISR. Failing to do so may cause undefined behavior of CPU execution. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 4 Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for either GPIO ASYNC or GPIO qualification. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 5 During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Boot ROM: Calling SCI Bootloader from Application SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 6 Advisory — During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer ..............Advisory — Boot ROM: Calling SCI Bootloader from Application TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 7 ........Advisory — Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 8 For simplicity, it is recommended that 500 µs be used as the power-up time for both CMPSS and GPDAC. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 9 1 (minimum) and 1023 (maximum) while observing the system clock on the XCLOCKOUT pin. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 10 // the ADCINTOVF here so the external routine will detect the // condition. AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; // clear OVF TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 11 The ADCxEVT can generate an ADCx_EVT interrupt to the PIE. The ISR can be used to Workaround(s) perform the desired task in software. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 12 For the revisions affected, when subsequent conversions switch between channel Workaround(s) groups, the S+H duration should be chosen to account for the additional capacitance. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 13 V will disable the internal VREG. This will not impact device operation. DDIO None Workaround(s) SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 14 All applications should follow the restrictions outlined in this advisory. Contact TI for Workaround(s) devices already in production which violate this advisory. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 15 Beginning with revision C silicon, the Boot ROM will perform the above workaround before branching to the application. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 16 Configure GPIO inputs configured as eQEP pins for non-asynchronous mode (any Workaround(s) GPxQSELn register option except “11b = Asynchronous”). TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 17 The workaround can also be applied at the System level by a supervisor resetting the device if it is not responding. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 18 // Delay of 120 SYSCLK Cycles The latest released C2000Ware, which has this workaround implemented, can be used as reference. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 19 If the number of samples is less than or equal to N, clear the SDIFLG register; otherwise, do not clear the SDIFLG register to prevent further SDFM interrupts. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 20 5. Enable the SDFM X-BAR trip events in the corresponding X-BAR registers (ePWM X- BAR or GPIO X-BAR event). TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 21 3. Delay for at least a latency of data filter + 5 SD-Cx clock cycles. 4. Enable the SDFM data filter. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 22 3p cycles to compute. Figure 4. Pipeline Diagram of the Issue When There are no Stalls in the Pipeline TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 23 ; FPU register read of R6H Figure 6 shows the pipeline diagram with the workaround in place. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 24 I5. There is no need to forward the result in this case. Figure 6. Pipeline Diagram With Workaround in Place TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 25 Do not clear the PIE IFR bits (that latch the LUF and LVF flags) directly because an interrupt event on the same PIE group (PIE group 12) may inadvertently be missed. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 26 // from an FPU operation (not EISQRTF32/EINVF32) // Handle Overflow/Underflow condition // Ack the interrupt and exit TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 27 C code, the user must consider these flags to be unreliable, and therefore, neither poll these flags in code nor trigger interrupts off of them. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 28 3. Use the external X1 and X2 crystal oscillators as the PLL clock source. The crystal oscillator does not have any drift related to V and V supply sequencing. DDOSC TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 29 This activity will be sufficient to consume the internal current. Workaround 3: An external 82-Ω resistor can be added to the board between V SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 30 SCL and SDA terminals. The placement of the series termination resistor and pullup resistor should be connected as shown in Figure TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 31 Maximum high-level input 3300 current up to 200 µA Maximum high-level input 6600 current up to 100 µA SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 32 2. Do not use DBRED/DBFED = 0 if in Shadow Load Mode. This is for both RED and FED. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 33 RPT #50 || NOP"); // Delay of 50 SYSCLK Cycles C2000Ware_3_00_00_00 and later revisions will have this workaround implemented. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 34 PWM duty cycle to a maximum value that will avoid simultaneous COMPSTS[COMPHSTS] and PWMSYNC assertions. TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 35 // To drive 0, set GPIO direction as output GpioCtrlRegs.GPxDIR.bit.GPIOx = 1; // To tri-state the GPIO(logic 1),set GPIO as input GpioCtrlRegs.GPxDIR.bit.GPIOx = 0; SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 36 If the order of the messages is critical to the application for processing, then this behavior will prevent the proper use of the DCAN FIFO mode. None Workaround(s) TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 37 Apply external clock source to X1 on silicon revision B devices, even if using INTOSC as Workaround(s) the application clock source. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...

  • Page 38: Documentation Support

    For more information regarding the TMS320F2807x devices, see the following documents: • TMS320F2807x Microcontrollers Data Manual • TMS320F2807x Microcontrollers Technical Reference Manual TMS320F2807x MCUs Silicon Revisions C, B SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 39 Documentation Support www.ti.com Trademarks PowerPAD, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. SPRZ423H – October 2014 – Revised February 2020 TMS320F2807x MCUs Silicon Revisions C, B Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...

  • Page 40: Revision History

    During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer ..........................advisory..........• Section 4.2: Added Boot ROM: Calling SCI Bootloader from Application advisory. Revision History SPRZ423H – October 2014 – Revised February 2020 Submit Documentation Feedback Copyright © 2014–2020, Texas Instruments Incorporated...
  • Page 41 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...