Altera Cyclone III User Manual page 16

4–2
Figure 4–1. Cyclone III Development Board Layout and Components
Switch (SW2)
Ethernet PHY
LEDs (D1, D3, D4)
Ethernet PHY
Duplex LED (D6)
Ethernet PHY TX/RX
Activity LEDS (D7, D8)
Speaker Header (J5)
125-MHz
Clock (Y4)
HSMC Port A (J8)
(Loopback Board Shown)
Clock In SMA (J10)
HSMC Port A
Present LED (D18)
Power Select
Rotary Switch (SW4)
User DIP
Switch (SW6)
Before powering up, prepare the board by performing the following steps:
1. If cards are plugged into the high-speed mezzanine connector (HSMC) ports,
2. Ensure that the POWER switch SW2 is in the OFF (or DOWN) position.
3. Configure the 8-position SW1 DIP switch to the default settings in
Table 4–1. Switch SW1 Settings (Part 1 of 2)
Cyclone III Development Kit User Guide
DDR2TOP_ACTIVE
LED (D11)
Power
LED (D5)
DDR2 SDRAM Device Interface
DC Power Four x16 and one x8
Power
Jack (J2) (U11, U12, U25, U26, U13)
(Three on Top and Two on Bottom)
User Push Buttons
(S1 through S4)
Power Display (U28)
CPU Reset Push
Button Switch (S5)
DDR2BOT_ACTIVE
LED (D16)
remove them (Figure 4–1) shows a daughter card plugged into both port A and
port B).
Switch Name
1 mW/mA
2 V/W
3 RSV0
4 RSV1
Cyclone III FPGA (U20)
MAX II Device
Control DIP
Switch (SW1)
Configuration
User LEDs
Done LED (D25)
(D26 through D33)
Graphics
Flash Active
LCD (J13)
LED (D23)
Function
Position 0
mW
V
MAX_RESERVE0
MAX_RESERVE1
Chapter 4: Development Board Setup
Powering Up the Board
MAX II CPLD (U7)
24-MHz Crystal (Y1)
6-MHz
Crystal (Y2)
JTAG Control
DIP Switch (SW3)
Device Select
Jumper (J6)
24-MHz USB-
Blaster Clock (Y3)
50-MHz
Clock (Y5)
HSMC Port B (J9)
(Debug Header Shown)
SRAM Active
LED (D17)
Clock Out SMA (J11)
HSMC Port B
Present LED (D19)
PGM Config Select
Rotary Switch (SW5)
Board-Specific LEDs
(D20 through D24)
User Defined
Reset and
7-Segment
Factory
Display (U30)
Configuration
Push Buttons
(S6 and S7)
Table
Default
Position 1 Position
mA
W
X
X
© March 2009 Altera Corporation
4–1.
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