Clu0Cf: Configurable Logic Unit 0 Configuration - Silicon Laboratories EFM8 Series Reference Manual

14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration

Bit 7
Name OUTSEL
Access RW
Reset 0
SFR Page = 0x20; SFR Address: 0xB1
Bit Name
7 OUTSEL
Value
0
1
6 OEN
This bit enables the asynchronous output of CLU0 to CLU0OUT.
Value
0
1
5:4 Reserved
3 RST
Writing this bit to 1 resets the D flip flop for CLU0. The bit will immediately return to 0.
Value
1
2 CLKINV
Value
0
1
1:0 CLKSEL
Value
0x0
0x1
0x2
0x3
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6 5
OEN Reserved
RW R
0 0x0
Reset Access
0 RW
Name
D_FF
LUT
0 RW
Name
DISABLE
ENABLE
Must write reset value.
0 RW
Name
RESET
0 RW
Name
NORMAL
INVERT
0x0 RW
Name
CARRY_IN
MXA_INPUT
ALTCLK0
ALTCLK1
Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)
4 3
RST
RW
0
Description
CLU Output Select.
Description
Select D flip-flop output of CLU
Select LUT output.
CLU Port Output Enable.
Description
Disables asynchronous output to the selected GPIO pin
Enables asynchronous output to the selected GPIO pin
CLU D flip-flop Reset.
Description
Reset the flip flop.
CLU D flip-flop Clock Invert.
Description
Clock signal is not inverted.
Clock signal will be inverted.
CLU D flip-flop Clock Selection.
Description
The carry-in signal.
The MXA input.
The alternate clock signal CLU0ALTCLK0.
The alternate clock signal CLU0ALTCLK1.
EFM8UB3 Reference Manual
2 1
CLKINV CLKSEL
RW RW
0 0x0
0
Rev. 0.2 | 175