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...the world's most energy friendly microcontrollers

EFM32TG Reference Manual

Tiny Gecko Series

• 32-bit ARM Cortex-M3 processor running at up to 32 MHz

• Up to 32 kB Flash and 4 kB RAM memory

• Energy efficient and autonomous peripherals

• Ultra low power Energy Modes with sub-µA operation

• Fast wake-up time of only 2 µs

The EFM32TG microcontroller series revolutionizes the 8- to 32-bit market with a

combination of unmatched performance and ultra low power consumption in both

active- and sleep modes. EFM32TG devices consume as little as 150 µA/MHz in run

mode, and as little as 1.0 µA with a Real Time Counter running, Brown-out and full

RAM and register retention.

EFM32TG's low energy consumption outperforms any other available 8-, 16-,

and 32-bit solution. The EFM32TG includes autonomous and energy efficient

peripherals, high overall chip- and analog integration, and the performance of the

industry standard 32-bit ARM Cortex-M3 processor.

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Summary of Contents for Silicon Laboratories EFM32TG

Page 1 EFM32TG devices consume as little as 150 µA/MHz in run mode, and as little as 1.0 µA with a Real Time Counter running, Brown-out and full RAM and register retention.
Page 2: Energy Friendly Microcontrollers
1 Energy Friendly Microcontrollers 1.1 Typical Applications The EFM32TG Tiny Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out of the available energy in a variety of applications.
Page 3: About This Document
This document contains reference material for the EFM32TG series of microcontrollers. All modules and peripherals in the EFM32TG series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin-out, are covered in the device-specific datasheets.
Page 4: Related Documentation
USn_TX (USARTn TX pin) The pin locations referenced in this document are given in the device-specific datasheet. 2.2 Related Documentation Further documentation on the EFM32TG family and the ARM Cortex-M3 can be found at the Silicon Laboratories and ARM web pages: www.silabs.com www.arm.com...
Page 5: System Overview
32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32TG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and low-energy consumption, see Figure 3.1 (p.
Page 6: Block Diagram
• TQFP48 • TQFP64 3.3 Block Diagram Figure 3.1 (p. 7) shows the block diagram of EFM32TG. The color indicates peripheral availability in the different energy modes, described in Section 3.4 (p. 7) . www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 7: Energy Modes
In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4. 3.4 Energy Modes There are five different Energy Modes (EM0-EM4) in the EFM32TG, see Table 3.1 (p. 8) . The EFM32TG is designed to achieve a high degree of autonomous operation in low energy modes. The...
Page 8: Product Overview
On Reset. All pins are put into their reset state. 3.5 Product Overview Table 3.2 (p. 8) shows a device overview of the EFM32TG Microcontroller Series, including peripheral functionality. For more information, the reader is referred to the device specific datasheets.
Page 9 ...the world's most energy friendly microcontrollers 110F4 1 (2) QFN24 110F8 1 (2) QFN24 110F16 1 (2) QFN24 110F32 1 (2) QFN24 210F8 1 (4) QFN32 210F16 1 (4) QFN32 210F32 1 (4) QFN32 222F8 1 (4) QFP48 (12) 222F16 1 (4) QFP48 (12)
Page 10: Device Revision
...the world's most energy friendly microcontrollers 840F32 1 (8) QFN64 842F8 1 (8) QFP64 842F16 1 (8) QFP64 842F32 1 (8) QFP64 3.6 Device Revision The device revision number is read from the ROM Table. The major revision number and the chip family number is read from PID0 and PID1 registers.
Page 11: System Processor
...the world's most energy friendly microcontrollers 4 System Processor Quick Facts What? The industry leading Cortex-M3 processor from ARM is the CPU in the EFM32TG microcontrollers. Why? The ARM Cortex-M3 is designed for exceptional short response time, high 0 1 2 3...
Page 12: Functional Description
Software generated interrupt The EFM32TG devices have up to 23 interrupt request lines (IRQ) which are connected to the Cortex- M3. Each of these lines (shown in Table 4.1 (p. 12) ) are connected to one or more interrupt flags in one or more modules.
Page 13 ...the world's most energy friendly microcontrollers IRQ # Source TIMER1 USART1_RX USART1_TX LESENSE LEUART0 LETIMER0 PCNT0 VCMP www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 14: Memory And Bus System
5.1 Introduction The EFM32TG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the master bus interfaces to the AHB slaves (Figure 5.1 (p. 15) ). The bus matrix allows several AHB slaves to be accessed simultaneously.
Page 15: Functional Description
...the world's most energy friendly microcontrollers Figure 5.1. EFM32TG Bus System Flash Cortex AHB Multilayer Bus Matrix ICode DCode System Peripheral 0 AHB/ APB Bridge Peripheral n 5.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Figure 5.2 (p.
Page 16: Memory Sram Area Set/Clear Bit
...the world's most energy friendly microcontrollers Figure 5.2. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32TG. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch instructions.
Page 17: Memory System Core Peripherals
...the world's most energy friendly microcontrollers bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (5.1) where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
Page 18 ...the world's most energy friendly microcontrollers Table 5.2. Memory System Low Energy Peripherals Low energy peripherals Address range Peripheral 0x4008A400 – 0x400BFFFF Reserved 0x4008C000 – 0x4008C3FF LESENSE 0x4008A000 – 0x4008A3FF 0x40088400 – 0x40089FFF Reserved 0x40088000 – 0x400883FF WDOG 0x40086C00 – 0x40087FFF Reserved 0x40086000 –...
Page 19 ...the world's most energy friendly microcontrollers Table 5.3. Memory System Peripherals Peripherals Address range Peripheral 0x40010C00 – 0x4007FFFF Reserved 0x40010400 – 0x400107FF TIMER1 0x40010000 – 0x400103FF TIMER0 0x4000E400 – 0x4000FFFF Reserved 0x4000CC00 – 0x4000DFFF Reserved 0x4000C400 – 0x4000C7FF USART1 0x4000C000 – 0x4000C3FF USART0 0x4000A400 –...
Page 20: Access To Low Energy Peripherals (Asynchronous Registers)
...the world's most energy friendly microcontrollers The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and the clock frequency. The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately. When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitration, is given by: Memory Wait Cycles with Clock Equal or Faster than HFCORECLK...
Page 21: Write Operation To Low Energy Peripherals
...the world's most energy friendly microcontrollers different synchronization mechanisms on the Tiny Gecko; immediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and results in an immediate update of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral being accessed.
Page 22 ...the world's most energy friendly microcontrollers is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however, always 0, indicating that register writes are always safe. Note If the application must be compatible with the EFM32G series, all Low Energy Peripherals should be accessed as if they only had delayed synchronization, i.e.
Page 23: Flash
...the world's most energy friendly microcontrollers 5.4 Flash The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash memory is typically programmed through the debug interface, but can also be erased and written to from software. •...
Page 24 ...the world's most energy friendly microcontrollers DI Address Register Description 0x0FE081B6 ADC0_CAL_2V5 [14:8]: Gain for 2V5 reference, [6:0]: Offset for 2V5 reference. 0x0FE081B8 ADC0_CAL_VDD [14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference. 0x0FE081BA ADC0_CAL_5VDIFF [14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF reference.
Page 25: Dbg - Debug Interface
6.1 Introduction The EFM32TG devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface. In addition, there is also a Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages.
Page 26: Debug Lock And Device Erase
...the world's most energy friendly microcontrollers • Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down. • Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up. •...
Page 27: Device Unlock
...the world's most energy friendly microcontrollers Figure 6.2. Device Unlock Reset Program ex ecution Locked No access Program 150 us ex ecution Unlocked No access Cortex Program 47 us ex ecution Ex tended No access Ex tended AAP Cortex unlocked 255 x 47 us Figure 6.3.
Page 28: Register Map
...the world's most energy friendly microcontrollers 6.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AAP_CMD Command Register 0x004 AAP_CMDKEY Command Key Register 0x008 AAP_STATUS Status Register 0x0FC AAP_IDR AAP Identification Register 6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset...
Page 29 ...the world's most energy friendly microcontrollers Name Reset Access Description The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command. Value Mode Description 0xCFACC118 WRITEEN...
Page 30: Msc - Memory System Controller
7.1 Introduction The Memory System Controller (MSC) is the program memory unit of the EFM32TG microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block.
Page 31: Features
...the world's most energy friendly microcontrollers 7.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M3 code interface • Zero wait-state access up to 16 MHz and one wait-state for 16 MHz and above • Advanced energy optimization functionality •...
Page 32: Lock Bits
...the world's most energy friendly microcontrollers Table 7.1. MSC Flash Memory Mapping Block Page Base address Write/Erase by Software Purpose/Name Size readable Main 0x00000000 Software, debug Yes User code and data 8 KB - 32 kB Software, debug Yes 0x00007E00 Software, debug Yes Reserved 0x00008000...
Page 33 ...the world's most energy friendly microcontrollers There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block. A page is locked when the bit is 0.
Page 34 ...the world's most energy friendly microcontrollers 7.3.4.4 Cortex-M3 If-Then Block Folding The Cortex-M3 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to false.
Page 35 ...the world's most energy friendly microcontrollers total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES. Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES). When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set.
Page 36 ...the world's most energy friendly microcontrollers It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed. Let us take as an example writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used: •...
Page 37: Register Map
...the world's most energy friendly microcontrollers 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register 0x00C MSC_WRITECMD Write Command Register...
Page 38 ...the world's most energy friendly microcontrollers 7.5.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICCDIS Interrupt Context Cache Disable Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context.
Page 39 ...the world's most energy friendly microcontrollers Name Reset Access Description When this bit is set to 1, any Cortex interrupt aborts any current page erase operation. Executing that interrupt vector from Flash will halt the CPU. WREN Enable Write/Erase Controller When this bit is set, the MSC write and erase functionality is enabled.
Page 40 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 ADDRB 0x00000000 Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set.
Page 41 ...the world's most energy friendly microcontrollers Name Reset Access Description When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA. INVADDR Invalid Write Address or Erase Page Set when software attempts to load an invalid (unmapped) address into ADDR.
Page 42 ...the world's most energy friendly microcontrollers Name Reset Access Description Set the CHOF flag and generate interrupt. WRITE Write Done Interrupt Set Set the write done bit and generate interrupt. ERASE Erase Done Interrupt Set Set the erase done bit and generate interrupt. 7.5.10 MSC_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 43 ...the world's most energy friendly microcontrollers Name Reset Access Description ERASE Erase Done Interrupt Enable Enable the erase done interrupt. 7.5.12 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000...
Page 44 ...the world's most energy friendly microcontrollers 7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CACHEHITS 0x00000...
Page 45 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PERIOD Sets the timebase period Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz AUXHFRCO band.
Page 46: Dma - Dma Controller
...the world's most energy friendly microcontrollers 8 DMA - DMA Controller Quick Facts What? The DMA controller can move data without 0 1 2 3 CPU intervention, effectively reducing the energy consumption for a data transfer. Why? The DMA can perform data transfers more energy efficiently than the CPU and allows Flash autonomous operation in low energy modes.
Page 47: Block Diagram
...the world's most energy friendly microcontrollers • Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length •...
Page 48: Functional Description
...the world's most energy friendly microcontrollers • A channel select block routing the right peripheral request to each DMA channel 8.4 Functional Description The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
Page 49 ...the world's most energy friendly microcontrollers and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 , that is, the controller arbitrates every 16 DMA transfers. Table 8.1 (p. 49) lists the arbitration rates. Table 8.1.
Page 50: Dma Cycle Types
...the world's most energy friendly microcontrollers Channel Priority level Descending order of number setting channel priority High High High High High Default Default Default Default Default Default Default Default Lowest-priority DMA channel After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 8.2 (p. 50) shows the process it uses to determine which DMA transfer to perform next.
Page 51 ...the world's most energy friendly microcontrollers Table 8.3. DMA cycle types cycle_ctrl Description b000 Channel control data structure is invalid b001 Basic DMA transfer b010 Auto-request b011 Ping-pong b100 Memory scatter-gather using the primary data structure b101 Memory scatter-gather using the alternate data structure b110 Peripheral scatter-gather using the primary data structure b111...
Page 52 ...the world's most energy friendly microcontrollers 2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at step 1 (p. 51) . 3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.
Page 53 ...the world's most energy friendly microcontrollers 5. The controller performs the remaining two DMA transfers. 6. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task C after task B completes, provided that a higher priority channel does not require servicing.
Page 54: Channel_Cfg For A Primary Data Structure, In Memory Scatter-Gather Mode
...the world's most energy friendly microcontrollers and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes. Note You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 52) , if you configure task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.
Page 55: Memory Scatter-Gather Example
...the world's most energy friendly microcontrollers Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy A, B, C, and D operations: cycle_ctrl = b100, 2 = 4, N = 16. 2. Write the prim ary source data to m em ory, using the structure shown in the following table. src_data_end_ptr dst_data_end_ptr channel_cfg...
Page 56: Channel_Cfg For A Primary Data Structure, In Peripheral Scatter-Gather Mode
...the world's most energy friendly microcontrollers 8. The controller generates an auto-request for the channel and then arbitrates. Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. Primary, copy D 10.
Page 57: Peripheral Scatter-Gather Example
...the world's most energy friendly microcontrollers Field Value Description [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 Configures the controller to perform N DMA transfers, where N is a multiple of four next_useburst When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes...
Page 58 ...the world's most energy friendly microcontrollers Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. Task A 2. The controller performs task A. 3. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B 4.
Page 59 ...the world's most energy friendly microcontrollers • provide a contiguous area of system memory that the controller and host processor can access • have a base address that is an integer multiple of the total size of the channel control data structure. Figure 8.6 (p.
Page 60 ...the world's most energy friendly microcontrollers Figure 8.7 (p. 60) shows a detailed memory map of the descriptor structure. Figure 8.7. Detailed memory map for the 8 channels, including the alternate data structure Unused 0x 0FC Control Alternate for 0x 0F8 channel 7 Destination End Pointer 0x 0F4...
Page 61: Channel_Cfg Bit Assignments
...the world's most energy friendly microcontrollers 8.4.3.2 Destination data end pointer The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Table 8.8 (p. 61) lists the bit assignments for this memory location. Table 8.8. dst_data_end_ptr bit assignments Name Description [31:0]...
Page 62 ...the world's most energy friendly microcontrollers Name Description b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains. [29:28] dst_size Destination data size. Note You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment.
Page 63 ...the world's most energy friendly microcontrollers Name Description b1000 Arbitrates after 256 DMA transfers. b1001 Arbitrates after 512 DMA transfers. b1010 - b1111 Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024. [13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers...
Page 64 ...the world's most energy friendly microcontrollers Name Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the primary data structure. b111 Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 56) . When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure.
Page 65: Examples
...the world's most energy friendly microcontrollers Table 8.11 (p. 65) lists the destination addresses for a DMA transfer of 12 bytes using a halfword increment. Table 8.11. DMA cycle of 12 bytes using a halfword increment Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer Count...
Page 66 ...the world's most energy friendly microcontrollers Example 8.1. DMA Transfer 1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) to src_data_end_ptr b.
Page 67: Register Map
...the world's most energy friendly microcontrollers 8.6 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DMA_STATUS DMA Status Registers 0x004 DMA_CONFIG DMA Configuration Register 0x008 DMA_CTRLBASE Channel Control Data Base Pointer Register 0x00C DMA_ALTCTRLBASE Channel Alternate Control Data Base Pointer Register...
Page 68: Register Description
...the world's most energy friendly microcontrollers 8.7 Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 CHNUM 0x07...
Page 69 ...the world's most energy friendly microcontrollers Name Reset Access Description Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 70 ...the world's most energy friendly microcontrollers 8.7.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7WAITSTATUS Channel 7 Wait on Request Status Status for wait on request for channel 7.
Page 71 ...the world's most energy friendly microcontrollers Name Reset Access Description CH5SWREQ Channel 5 Software Request Write 1 to this bit to generate a DMA request for this channel. CH4SWREQ Channel 4 Software Request Write 1 to this bit to generate a DMA request for this channel. CH3SWREQ Channel 3 Software Request Write 1 to this bit to generate a DMA request for this channel.
Page 72 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SINGLEANDBURST Channel responds to both single and burst requests BURSTONLY Channel responds to burst requests only 8.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register Offset Bit Position 0x01C Reset Access Name...
Page 73 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7REQMASKS Channel 7 Request Mask Set Write to 1 to disable peripheral requests for this channel. CH6REQMASKS Channel 6 Request Mask Set Write to 1 to disable peripheral requests for this channel.
Page 74 ...the world's most energy friendly microcontrollers Name Reset Access Description CH0REQMASKC Channel 0 Request Mask Clear Write to 1 to enable peripheral requests for this channel. 8.7.11 DMA_CHENS - Channel Enable Set Register Offset Bit Position 0x028 Reset Access Name Name Reset Access...
Page 75 ...the world's most energy friendly microcontrollers Name Reset Access Description CH7ENC Channel 7 Enable Clear Write to 1 to disable this channel. See also description for channel 0. CH6ENC Channel 6 Enable Clear Write to 1 to disable this channel. See also description for channel 0. CH5ENC Channel 5 Enable Clear Write to 1 to disable this channel.
Page 76 ...the world's most energy friendly microcontrollers Name Reset Access Description CH0ALTS Channel 0 Alternate Structure Set Write to 1 to select the alternate structure for this channel. 8.7.14 DMA_CHALTC - Channel Alternate Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset...
Page 77 ...the world's most energy friendly microcontrollers Name Reset Access Description CH7PRIS Channel 7 High Priority Set Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH6PRIS Channel 6 High Priority Set Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH5PRIS Channel 5 High Priority Set Write to 1 to obtain high priority for this channel.
Page 78 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear high priority for this channel. 8.7.17 DMA_ERRORC - Bus Error Clear Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 79 ...the world's most energy friendly microcontrollers Name Reset Access Description When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 DMA transfers.
Page 80 ...the world's most energy friendly microcontrollers 8.7.20 DMA_IF - Interrupt Flag Register Offset Bit Position 0x1000 Reset Access Name Name Reset Access Description DMA Error Interrupt Flag This flag is set when an error has occurred on the AHB bus. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 81 ...the world's most energy friendly microcontrollers Name Reset Access Description CH6DONE DMA Channel 6 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag. CH5DONE DMA Channel 5 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag. CH4DONE DMA Channel 4 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag.
Page 82 ...the world's most energy friendly microcontrollers 8.7.23 DMA_IEN - Interrupt Enable register Offset Bit Position 0x100C Reset Access Name Name Reset Access Description DMA Error Interrupt Flag Enable Set this bit to enable interrupt on AHB bus error. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 83 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b000000 NONE No source selected 0b001000 ADC0 Analog to Digital Converter 0 0b001010 DAC0 Digital to Analog Converter 0 0b001100 USART0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 0b001101 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1 0b010000 LEUART0...
Page 84 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b0011 TIMER1CC2 TIMER1CC2 SOURCESEL = 0b110000 (MSC) 0b0000 MSCWDATA MSCWDATA SOURCESEL = 0b110001 (AES) 0b0000 AESDATAWR AESDATAWR 0b0001 AESXORDATAWR AESXORDATAWR 0b0010 AESDATARD AESDATARD 0b0011 AESKEYWR AESKEYWR SOURCESEL 0b110010 (LESENSE) 0b0000...
Page 85: Rmu - Reset Management Unit
• A software readable register indicates the cause of the last reset 9.3 Functional Description The RMU monitors each of the reset sources of the EFM32TG. If one or more reset sources go active, the RMU applies reset to the EFM32TG. When the reset sources go inactive the EFM32TG starts up.
Page 86 ...the world's most energy friendly microcontrollers As seen in Figure 9.1 (p. 86) the Power-on Reset, Brown-out Detectors, Watchdog timeout and RESETn pin all reset the whole system including the Debug Interface. A Core Lockup condition or a System reset request from software resets the whole system except the Debug Interface. Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set.
Page 87 VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EFM32TG is kept in reset state. The operation of the POR is illustrated in Figure 9.2 (p. 87) , with the active low POWERONn reset signal. The reason for the “unknown”...
Page 88 9.3.4 RESETn pin Reset Forcing the RESETn pin low generates a reset of the EFM32TG. The RESETn pin includes an on- chip pull-up resistor, and can therefore be left unconnected if no external reset source is needed. Also connected to the RESETn line is a filter which prevents glitches from resetting the EFM32TG.
Page 89: Register Map
...the world's most energy friendly microcontrollers 9.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE Reset Cause Register 0x008 RMU_CMD Command Register 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset Bit Position...
Page 90 ...the world's most energy friendly microcontrollers Name Reset Access Description EM4RST EM4 Reset Set if the system has been in EM4. Must be cleared by software. Please see Table 9.1 (p. 87) for details on how to interpret this bit. SYSREQRST System Request Reset Set if a system request reset has been performed.
Page 91: Emu - Energy Management Unit
10.1 Introduction The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32TG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The energy modes range from EM0 to EM4, where EM0, also called run mode, enables the CPU and all peripherals.
Page 92: Functional Description
10.3 Functional Description The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32TG. An overview of the EMU module is shown in Figure 10.1 (p. 92) . Figure 10.1. EMU Overview Peripheral bus...
Page 93 ...the world's most energy friendly microcontrollers Figure 10.2. EMU Energy Mode Transitions Active m ode Low energy m odes No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p. 93) . Instead, a wakeup will transition back to EM0, in which software can enter any other low energy mode.
Page 94 ...the world's most energy friendly microcontrollers Table 10.1. EMU Energy Mode Overview Wakeup time to EM0 2 µs 2 µs 160 µs MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator C full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter LEUART...
Page 95 ...the world's most energy friendly microcontrollers 10.3.1.3 EM2 • The high frequency oscillator is inactive • The high frequency peripheral and MCU clock trees are inactive • The low frequency oscillator and clock trees are active • Low frequency peripheral functionality is available •...
Page 96 ...the world's most energy friendly microcontrollers (‘x’ means don’t care) 10.3.3 Leaving a Low Energy Mode In each low energy mode a selection of peripheral units are available, and software can either enable or disable the functionality. Enabled interrupts that can cause wakeup from a low energy mode are shown in Table 10.3 (p.
Page 97: Register Map
...the world's most energy friendly microcontrollers 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x008 EMU_LOCK Configuration Lock Register 0x024 EMU_AUXCTRL Auxiliary Control Register 10.5 Register Description 10.5.1 EMU_CTRL - Control Register Offset Bit Position...
Page 98 ...the world's most energy friendly microcontrollers Name Reset Access Description 15:0 LOCKKEY 0x0000 Configuration Lock Key Write any other value than the unlock code to lock all EMU registers, except the interrupt registers, from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled. Mode Value Description...
Page 99: Cmu - Clock Management Unit
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32TG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.
Page 100: Functional Description
...the world's most energy friendly microcontrollers • Clock Gating on an individual basis to core modules and all peripherals • Selectable clocks can be output on two pins for use externally. • Auxiliary 1-28 MHz RC oscillator (AUXHFRCO) for flash programming, debug trace, and LESENSE timing.
Page 101: Cmu Overview
...the world's most energy friendly microcontrollers Figure 11.1. CMU Overview LESENSE (High frequency tim ing) (Flash Program m ing) AUXCLK AUXHFRCO Tim eout Debug Trace CMU_CTRL_DBGCLK clock switch CMU_HFPERCLKEN0.TIMER0 Clock HFPERCLK TIMER0 Gate CMU_HFPERCLKEN0.TIMER1 HFPERCLK Clock TIMER1 Gate CMU_HFPERCLKDIV.HFPERCLKEN HFPERCLK prescaler CMU_HFPERCLKEN0.I2C0 CMU_HFPERCLKDIV.HFPERCLKDIV...
Page 102 ...the world's most energy friendly microcontrollers 11.3.1 System Clocks 11.3.1.1 HFCLK - High Frequency Clock HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK and HFPERCLK. The HFCLK can be driven by a high-frequency oscillator (HFRCO or HFXO) or one of the low-frequency oscillators (LFRCO or LFXO).
Page 103 ...the world's most energy friendly microcontrollers 11.3.1.5 LFBCLK - Low Frequency B Clock LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFBCLK can be disabled. From reset, the LFBCLK source is set to LFRCO.
Page 104: Cmu Switching From Hfrco To Hfxo Before Hfxo Is Ready
...the world's most energy friendly microcontrollers 11.3.2.2 Switching Clock Source The HFRCO oscillator is a low energy oscillator with extremely short wake-up time. Therefore, this oscillator is always chosen by hardware as the clock source for HFCLK when the device starts up (e.g. after reset and after waking up from EM2 and EM3).
Page 105: Cmu Switching From Hfrco To Hfxo After Hfxo Is Ready
...the world's most energy friendly microcontrollers Figure 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO HFXO tim e- out period Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL.
Page 106 ...the world's most energy friendly microcontrollers Figure 11.5. LFXO Pin Connection LFXTAL_N LFXTAL_P 32.768kHz EFM32 It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed.
Page 107: Continuous Calibration (Cont=1)
...the world's most energy friendly microcontrollers Figure 11.6. HW-support for RC Oscillator Calibration DOWNCLK Dom ain Reload down- counter with top value in continouous m ode. CMU_CALCTRL.DOWNSEL AUXHFRCO HFRCO Write top- value using LFRCO DOWNCLK CMU_CALCNT before 20- bit down- counter HFXO starting calibration.
Page 108 ...the world's most energy friendly microcontrollers 11.3.4 Output Clock on a Pin It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1 fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE register.
Page 109: Register Map
...the world's most energy friendly microcontrollers 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x004 CMU_HFCORECLKDIV High Frequency Core Clock Division Register 0x008 CMU_HFPERCLKDIV High Frequency Peripheral Clock Division Register 0x00C CMU_HFRCOCTRL HFRCO Control Register...
Page 110: Register Description
...the world's most energy friendly microcontrollers 11.5 Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DBGCLK Debug Clock Select clock used for the debug system.
Page 111 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 16KCYCLES Timeout period of 16384 cycles. 32KCYCLES Timeout period of 32768 cycles. LFXOBUFCUR LFXO Boost Buffer Current This value has been updated to the correct level during calibration and should not be changed. 16:14 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 112 ...the world's most energy friendly microcontrollers 11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HFCORECLKDIV HFCORECLK Divider Specifies the clock divider for HFCORECLK.
Page 113 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description HFCLK HFPERCLK = HFCLK. HFCLK2 HFPERCLK = HFCLK/2. HFCLK4 HFPERCLK = HFCLK/4. HFCLK8 HFPERCLK = HFCLK/8. HFCLK16 HFPERCLK = HFCLK/16. HFCLK32 HFPERCLK = HFCLK/32. HFCLK64 HFPERCLK = HFCLK/64. HFCLK128 HFPERCLK = HFCLK/128.
Page 114 ...the world's most energy friendly microcontrollers 11.5.5 CMU_LFRCOCTRL - LFRCO Control Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) TUNING 0x40 LFRCO Tuning Value...
Page 115 ...the world's most energy friendly microcontrollers 11.5.7 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CONT Continuous Calibration Set this bit to enable continuous calibration.
Page 116 ...the world's most energy friendly microcontrollers Name Reset Access Description 19:0 CALCNT 0x00000 Calibration Counter Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set. 11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset Bit Position 0x020...
Page 117 ...the world's most energy friendly microcontrollers 11.5.10 CMU_CMD - Command Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CALSTOP Calibration Stop Stops the calibration counters.
Page 118 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ULFRCO ULFRCO selected as LFACLK (when LFA = DISABLED). 15:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Clock Select for LFB Selects the clock source for LFBCLK.
Page 119 ...the world's most energy friendly microcontrollers Name Reset Access Description LFXOENS LFXO Enable Status LFXO is enabled. LFRCORDY LFRCO Ready LFRCO is enabled and start-up time has exceeded. LFRCOENS LFRCO Enable Status LFRCO is enabled. AUXHFRCORDY AUXHFRCO Ready AUXHFRCO is enabled and start-up time has exceeded. AUXHFRCOENS AUXHFRCO Enable Status AUXHFRCO is enabled.
Page 120 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when HFRCO is ready (start-up time exceeded). 11.5.14 CMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CALOF Calibration Overflow Interrupt Flag Set Write to 1 to set the Calibration Overflow Interrupt Flag.
Page 121 ...the world's most energy friendly microcontrollers Name Reset Access Description CALOF Calibration Overflow Interrupt Flag Clear Write to 1 to clear the Calibration Overflow Interrupt Flag. CALRDY Calibration Ready Interrupt Flag Clear Write to 1 to clear the Calibration Ready Interrupt Flag. AUXHFRCORDY AUXHFRCO Ready Interrupt Flag Clear Write to 1 to clear the AUXHFRCO Ready Interrupt Flag.
Page 122 ...the world's most energy friendly microcontrollers 11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Low Energy Peripheral Interface Clock Enable Set to enable the clock for LE.
Page 123 ...the world's most energy friendly microcontrollers Name Reset Access Description TIMER1 Timer 1 Clock Enable Set to enable the clock for TIMER1. TIMER0 Timer 0 Clock Enable Set to enable the clock for TIMER0. USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable Set to enable the clock for USART1.
Page 124 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description CMU_LFACLKEN0 is ready for update. CMU_LFACLKEN0 is busy synchronizing new value. 11.5.20 CMU_FREEZE - Freeze Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 125: Lcd
...the world's most energy friendly microcontrollers 11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LEUART0 Low Energy UART 0 Clock Enable Set to enable the clock for LEUART0.
Page 126 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV1024 LFACLK = LFACLK/1024 LETIMER0 DIV2048 LFACLK = LFACLK/2048 LETIMER0 DIV4096 LFACLK = LFACLK/4096 LETIMER0 DIV8192 LFACLK = LFACLK/8192 LETIMER0 DIV16384 LFACLK = LFACLK/16384 LETIMER0 DIV32768 LFACLK = LFACLK/32768 LETIMER0 Real-Time Counter Prescaler...
Page 127 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV1 LFBCLK = LFBCLK LEUART0 DIV2 LFBCLK = LFBCLK/2 LEUART0 DIV4 LFBCLK = LFBCLK/4 LEUART0 DIV8 LFBCLK = LFBCLK/8 LEUART0 11.5.25 CMU_PCNTCTRL - PCNT Control Register Offset Bit Position 0x078 Reset...
Page 128 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV4 Voltage Boost update Frequency = LFACLK/4. DIV8 Voltage Boost update Frequency = LFACLK/8. DIV16 Voltage Boost update Frequency = LFACLK/16. DIV32 Voltage Boost update Frequency = LFACLK/32. DIV64 Voltage Boost update Frequency = LFACLK/64.
Page 129 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000 Configuration Lock Key Write other value than unlock code lock...
Page 130: Wdog - Watchdog Timer
...the world's most energy friendly microcontrollers 12 WDOG - Watchdog Timer Quick Facts What? The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can 0 1 2 3 be enabled in all energy modes as long as the low frequency clock source is available.
Page 131: Wdog Timeout Equation
...the world's most energy friendly microcontrollers 12.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected clocks.
Page 132: Register Map
...the world's most energy friendly microcontrollers 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 133 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SWOSCBLOCK Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.
Page 134 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLEAR Watchdog Timer Clear Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout. Value Mode Description...
Page 135: Prs - Peripheral Reflex System
...the world's most energy friendly microcontrollers 13 PRS - Peripheral Reflex System Quick Facts What? 0 1 2 3 The PRS (Peripheral Reflex System) allows configurable, fast and autonomous communication between the peripherals. Why? Events and signals from one peripheral can be used as input signals or triggers by other peripherals and ensure timing-critical Tim er...
Page 136: Prs Overview
...the world's most energy friendly microcontrollers 13.3.1 Asynchronous Mode Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can be used as an input to all reflex consumers, but since they require HFPERCLK, they will not work in EM2/EM3.
Page 137 ...the world's most energy friendly microcontrollers Table 13.1. Reflex Producers Module Reflex Output Output Format Async Support ACMP Comparator Output Level Single Conversion Done Pulse Scan Conversion Done Pulse Channel 0 Conversion Pulse Done Channel 1 Conversion Pulse Done GPIO Pin 0 Input Level Pin 1 Input...
Page 138 ...the world's most energy friendly microcontrollers Module Reflex Output Output Format Async Support IrDA Decoder Output Level VCMP Comparator Output Level LESENSE SCANRES register Level Decoder Output Level/Pulse 13.3.4 Consumers Consumer peripherals (listed in Table 13.2 (p. 138) ) can be set to listen to a PRS channel and perform an action based on the signal received on that channel.
Page 139 ...the world's most energy friendly microcontrollers • Configure ADC0 with the desired conversion set-up. • Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal. • Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion.
Page 140: Register Map
...the world's most energy friendly microcontrollers 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_SWPULSE Software Pulse Register 0x004 PRS_SWLEVEL Software Level Register 0x008 PRS_ROUTE I/O Routing Register 0x010 PRS_CH0_CTRL Channel Control Register 0x014...
Page 141 ...the world's most energy friendly microcontrollers 13.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7LEVEL Channel 7 Software Level See bit 0.
Page 142 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH3PEN CH3 Pin Enable When set, GPIO output from PRS channel 3 is enabled CH2PEN CH2 Pin Enable When set, GPIO output from PRS channel 2 is enabled...
Page 143 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b101000 Real-Time Counter 0b110000 GPIOL General purpose Input/Output 0b110001 GPIOH General purpose Input/Output 0b110100 LETIMER0 Low Energy Timer 0 0b111001 LESENSEL Low Energy Sensor Interface 0b111010 LESENSEH Low Energy Sensor Interface 0b111011 LESENSED...
Page 144 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SOURCESEL = 0b110000 (GPIO) 0b000 GPIOPIN0 GPIO pin 0 GPIOPIN0 0b001 GPIOPIN1 GPIO pin 1 GPIOPIN1 0b010 GPIOPIN2 GPIO pin 2 GPIOPIN2 0b011 GPIOPIN3 GPIO pin 3 GPIOPIN3 0b100 GPIOPIN4 GPIO pin 4 GPIOPIN4...
Page 145: I 2 C - Inter-Integrated Circuit Interface
...the world's most energy friendly microcontrollers 14 I C - Inter-Integrated Circuit Interface Quick Facts What? 0 1 2 3 The I C interface allows communication on I C-buses with the lowest energy consumption possible. Why? EFM32 C m aster/ slave C is a popular serial bus that enables communication with a number of external devices using only two I/O pins.
Page 146: Functional Description
...the world's most energy friendly microcontrollers 14.3 Functional Description An overview of the I C module is shown in Figure 14.1 (p. 146) . Figure 14.1. I C Overview Peripheral Bus C Control and Transm it Buffer Receive Buffer Status I2Cn_SDA Sym bol Transm it...
Page 147: C Start And Stop Conditions
...the world's most energy friendly microcontrollers Note If V drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low. 14.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus.
Page 148 ...the world's most energy friendly microcontrollers on the bus can try to gain control of it. If the current master wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START condition (Sr) instead of a STOP followed by a START.
Page 149 ...the world's most energy friendly microcontrollers 14.3.1.4 10-bit Addressing To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address.
Page 150: C High And Low Periods For Low Clkdiv
...the world's most energy friendly microcontrollers 14.3.3 Safely Disabling and Changing Slave Configuration The I C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configuration change. These measures should be taken, if (while the slave is enabled) the user cannot guarantee that an address match will not occur at the exact time of slave disable or slave configuration change.
Page 151 ...the world's most energy friendly microcontrollers Table 14.3. I C Clock Mode HFPERCLK Clock Low High Sm max frequency Fm max frequency Fm+ max frequency frequency (MHz) Ratio (CLHR) (kHz) (kHz) (kHz) 1000 1000 1000 14.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value.
Page 152 ...the world's most energy friendly microcontrollers transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded into the shift register. The byte is then kept in the shift register until it is transmitted. When a byte has been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer).
Page 153: C Master State Machine
...the world's most energy friendly microcontrollers After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data to the slave.
Page 154: C Interactions In Prioritized Order
...the world's most energy friendly microcontrollers 14.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module.
Page 155 ...the world's most energy friendly microcontrollers set in a pending state, which can be read from the STATUS register. A pending START command can for instance be identified by PSTART having a high value. Whenever the I C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an interaction, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get an interaction from software.
Page 156 ...the world's most energy friendly microcontrollers value of I2Cn_STATE will then be 0x57. As seen in the table, the I C module also stops in this state if the address is not available after a repeated start condition. To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit cleared (ADDR+W).
Page 157 ...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START Repeated start condition will be sent STOP + STOP will be sent and the bus released. Then START a START will be sent when the bus becomes idle Data transmitted TXBL interrupt flag...
Page 158 ...the world's most energy friendly microcontrollers As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.
Page 159 ...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt None flag START START will be sent when bus becomes idle 14.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time.
Page 160: C Slave State Machine
...the world's most energy friendly microcontrollers 14.3.9.1 Slave State Machine The slave state machine is shown in Figure 14.11 (p. 160) . The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.
Page 161 ...the world's most energy friendly microcontrollers 14.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit.
Page 162 ...the world's most energy friendly microcontrollers Table 14.9. I C Slave Transmitter I2Cn_STATE Description I2Cn_IF Required Response interaction 0x41 Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x75 ADDR + R received ADDR interrupt flag ACK + ACK will be sent, then DATA TXDATA...
Page 163 ...the world's most energy friendly microcontrollers See Table 14.10 (p. 163) for more information. Table 14.10. I C - Slave Receiver I2Cn_STATE Description I2Cn_IF Required Response interaction Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x71 ADDR + W received...
Page 164 ...the world's most energy friendly microcontrollers 14.3.11 Using 10-bit Addresses When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two most significant bits are correct.
Page 165 ...the world's most energy friendly microcontrollers Many slave-only devices operating on an I C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to make them release SCL.
Page 166 ...the world's most energy friendly microcontrollers • Transmit buffer and shift register empty. No data to send • Transmit buffer empty 14.3.14 Interrupts The interrupts generated by the I C module are combined into one interrupt vector, I2C_INT. If I interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.
Page 167: Register Map
...the world's most energy friendly microcontrollers 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS Status Register 0x010 I2Cn_CLKDIV Clock Division Register...
Page 168 ...the world's most energy friendly microcontrollers Name Reset Access Description When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Description A bus idle timeout has no effect on the bus state. A bus idle timeout tells the I C module that the bus is idle, allowing new transfers to be initiated.
Page 169 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description Software must give one ACK command for each ACK transmitted on the I C bus. Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. SLAVE Addressable as Slave Set this bit to allow the device to be selected as an I C slave.
Page 170 ...the world's most energy friendly microcontrollers 14.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) STATE Transmission State The state of any current transmission.
Page 171 ...the world's most energy friendly microcontrollers Name Reset Access Description RXDATAV RX Data Valid Set when data is available in the receive buffer. Cleared when the receive buffer is empty. TXBL TX Buffer Level Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full. TX Complete Set when a transmission has completed and no more data is available in the transmit buffer.
Page 172 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ADDR 0x00 Slave address Specifies the slave address of the device. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 173 ...the world's most energy friendly microcontrollers 14.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAP 0x00 RX Data Peek...
Page 174 ...the world's most energy friendly microcontrollers Name Reset Access Description Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register. BITO Bus Idle Timeout Interrupt Flag Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register. RXUF Receive Buffer Underflow Interrupt Flag Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
Page 175 ...the world's most energy friendly microcontrollers Name Reset Access Description SSTOP Set SSTOP Interrupt Flag Write to 1 to set the SSTOP interrupt flag. CLTO Set Clock Low Interrupt Flag Write to 1 to set the CLTO interrupt flag. BITO Set Bus Idle Timeout Interrupt Flag Write to 1 to set the BITO interrupt flag.
Page 176 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear the SSTOP interrupt flag. CLTO Clear Clock Low Interrupt Flag Write to 1 to clear the CLTO interrupt flag. BITO Clear Bus Idle Timeout Interrupt Flag Write to 1 to clear the BITO interrupt flag.
Page 177 ...the world's most energy friendly microcontrollers Name Reset Access Description CLTO Clock Low Interrupt Enable Enable interrupt on clock low timeout. BITO Bus Idle Timeout Interrupt Enable Enable interrupt on bus idle timeout. RXUF Receive Buffer Underflow Interrupt Enable Enable interrupt on receive buffer underflow. TXOF Transmit Buffer Overflow Interrupt Enable Enable interrupt on transmit buffer overflow.
Page 178 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:8 LOCATION I/O Location Decides the location of the I C I/O pins. Value Mode Description LOC0 Location 0 LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6...
Page 179: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 15 USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? 0 1 2 3 The USART handles high-speed UART, SPI- bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embedded systems and the USART allows controller efficient communication with a wide range of external devices.
Page 180: Functional Description
...the world's most energy friendly microcontrollers • HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection • Multi-processor mode • IrDA modulator on USART0 • SmartCard (ISO7816) mode •...
Page 181: Usart Asynchronous Frame Format
...the world's most energy friendly microcontrollers Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported protocols in Table 15.1 (p. 181) . Full duplex and half duplex communication is supported in both asynchronous and synchronous mode. Table 15.1.
Page 182: Usart Data Bits
...the world's most energy friendly microcontrollers Table 15.3. USART Data Bits DATA BITS [3:0] Number of Data bits 0001 0010 0011 0100 0101 8 (Default) 0110 0111 1000 1001 1010 1011 1100 1101 Table 15.4. USART Stop Bits STOP BITS [1:0] Number of Stop bits 1 (Default) The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL.
Page 183: Usart Baud Rate
...the world's most energy friendly microcontrollers Table 15.5. USART Parity Bits STOP BITS [1:0] Description No parity bit (Default) Reserved Even parity Odd parity 15.3.2.2 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Equation 15.1 (p.
Page 184 ...the world's most energy friendly microcontrollers Table 15.7. USART Baud Rates @ 4MHz Peripheral Clock USARTn_OVS =00 USARTn_OVS =01 Desired baud rate Actual baud Actual baud USARTn_CLKDIV/256 Error % USARTn_CLKDIV/256 Error % [baud/s] rate [baud/s] rate [baud/s] 415,75 599,88 -0,02 832,25 600,06 0,01...
Page 185 ...the world's most energy friendly microcontrollers frames, complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the 9th bits that are transmitted if 9-bit frames are used.
Page 186 ...the world's most energy friendly microcontrollers • Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the transmitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always read as 0. Note When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure.
Page 187 ...the world's most energy friendly microcontrollers The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits is shown in Figure 15.4 (p. 187) . Figure 15.4. USART Receive Buffer Operation Peripheral Bus RXDOUBLE RXDATA, RXDOUBLEX...
Page 188: Usart Sampling Of Start And Data Bits
...the world's most energy friendly microcontrollers When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame. For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity.
Page 189: Usart Sampling Of Stop Bits When Number Of Stop Bits Are 1 Or More
...the world's most energy friendly microcontrollers Figure 15.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/ 1 0/ 1 0/ 1 0/ 1...
Page 190 ...the world's most energy friendly microcontrollers can receive the data it transmits, but it is also used to allow the USART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX pin must be enabled as an output in the GPIO.
Page 191 ...the world's most energy friendly microcontrollers This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AUTOCS in USARTn_CTRL is set, the USn_CS output is automatically activated one baud period before the transmitter starts transmitting data, and deactivated when the last bit has been transmitted and there is no more data in the transmit buffer to transmit, or the transmitter becomes disabled.
Page 192: Usart Transmission Of Large Frames
...the world's most energy friendly microcontrollers Figure 15.9. USART Transmission of Large Frames Peripheral Bus TX buffer elem ent 1 Write CTRL TX buffer elem ent 0 Write CTRL Shift register Write CTRL As shown in Figure 15.9 (p. 192) , frame transmission control bits are taken from the second element in FIFO.
Page 193 ...the world's most energy friendly microcontrollers Figure 15.11. USART Reception of Large Frames Peripheral Bus RX buffer elem ent 0 Status RX buffer elem ent 1 Status Shift register Status The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register.
Page 194: Usart Iso 7816 Data Frame Without Error
...the world's most energy friendly microcontrollers BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and 8-bit writes to the USART can be used when writing the data frames.
Page 195: Usart Iso 7816 Data Frame With Error
...the world's most energy friendly microcontrollers Figure 15.13. USART ISO 7816 Data Frame With Error ISO 7816 Fram e with error Start or idle Stop or idle Stop Stop On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame.
Page 196: Usart Spi Modes
...the world's most energy friendly microcontrollers 15.3.3.1 Frame Format The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the communication. Parity bits cannot be used in synchronous mode. The USART supports frame lengths of 4 to 16 bits per frame.
Page 197 ...the world's most energy friendly microcontrollers Figure 15.15. USART SPI Timing CLKPOL = 0 USn_CLK CLKPOL = 1 USn_CS CLKPHA = 0 USn_TX/ USn_RX CLKPHA = 1 If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available.
Page 198 ...the world's most energy friendly microcontrollers When AUTOTX in USARTn_CTRL is set, the USART transmits data as long as there is available space in the RX shift register for the chosen frame size. This happens even though there is no data in the TX buffer.
Page 199: Usart Standard I2S Waveform
...the world's most energy friendly microcontrollers whether the transmitted word is for the left or right audio channel; A word transmitted while the word clock is low is for the left channel, and a word transmitted while the word clock is high is for the right. When operating in I2S mode, the CS pin is used as a the word clock.
Page 200 ...the world's most energy friendly microcontrollers Figure 15.17. USART Standard I2S waveform (reduced accuracy) USn_CLK USn_CS (word select) USn_TX/ USn_RX Right channel Left channel Right channel A left-justified stream is shown in Figure 15.18 (p. 200) . Note that the MSB comes directly after the edge on the word-select signal in contradiction to the regular I2S waveform where it comes one bit- period after.
Page 201 ...the world's most energy friendly microcontrollers In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each word. Mono I2S waveform is shown in Figure 15.20 (p. 201) . Figure 15.20. USART Mono I2S waveform USn_CLK USn_CS (word select)
Page 202 ...the world's most energy friendly microcontrollers TX buffer with the command and enable AUTOTXTEN and TXTEN. When the selected PRS input goes high, the USART will now transmit the loaded command, and then continue clocking out while both the PRS input is high and there is room in the RX buffer 15.3.5 PRS RX Input The USART can be configured to receive data directly from a PRS channel by setting RXPRS in USARTn_INPUT.
Page 203 ...the world's most energy friendly microcontrollers The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags: • TXC • TXBL • TXOF • CCF The reception interrupt on the other hand groups the reception-related interrupts, triggered by the following interrupt flags: •...
Page 204 ...the world's most energy friendly microcontrollers Table 15.10. USART IrDA Pulse Widths IRPW Pulse width OVS=0 Pulse width OVS=1 Pulse width OVS=2 Pulse width OVS=3 1/16 2/16 3/16 4/16 By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL.
Page 205: Register Map
...the world's most energy friendly microcontrollers 15.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control register 0x00C USARTn_CMD Command Register...
Page 206 ...the world's most energy friendly microcontrollers Name Reset Access Description Transmits as long as RX is not full. If TX is empty, underflows are generated. BYTESWAP Byteswap In Double Accesses Set to switch the order of the bytes in double accesses. Value Description Normal byte order...
Page 207 ...the world's most energy friendly microcontrollers Name Reset Access Description Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave. Value Description Chip select is active low Chip select is active high TXINV Transmitter output Invert...
Page 208 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Double speed with 8X oversampling in asynchronous mode 6X oversampling in asynchronous mode Quadruple speed with 4X oversampling in asynchronous mode MPAB Multi-Processor Address-Bit Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.
Page 209 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description The transmitter generates two stop bits. The receiver checks the first stop-bit only 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used.
Page 210 ...the world's most energy friendly microcontrollers Name Reset Access Description Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN. Value Mode Description PRSCH0 PRS Channel 0 selected PRSCH1 PRS Channel 1 selected PRSCH2 PRS Channel 2 selected...
Page 211 ...the world's most energy friendly microcontrollers Name Reset Access Description RXEN Receiver Enable Set to activate data reception on U(S)n_RX. 15.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXFULLRIGHT RX Full of Right Data When set, the entire RX buffer contains right data.
Page 212 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the receiver is enabled. 15.5.6 USARTn_CLKDIV - Clock Control Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:6 0x0000 Fractional Clock Divider...
Page 213 ...the world's most energy friendly microcontrollers 15.5.8 USARTn_RXDATA - RX Buffer Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATA 0x00 RX Data...
Page 214 ...the world's most energy friendly microcontrollers 15.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:8 RXDATA1 0x00...
Page 215 ...the world's most energy friendly microcontrollers 15.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
Page 216 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to disable transmitter and release data bus directly after transmission. TXBREAK Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of WDATA.
Page 217 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to disable transmitter and release data bus directly after transmission. TXBREAK1 Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of USARTn_WDATA.
Page 218 ...the world's most energy friendly microcontrollers 15.5.17 USARTn_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Collision Check Fail Interrupt Flag Set when a collision check notices an error in the transmitted data.
Page 219 ...the world's most energy friendly microcontrollers 15.5.18 USARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Set Collision Check Fail Interrupt Flag Write to 1 to set the CCF interrupt flag.
Page 220 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Clear Collision Check Fail Interrupt Flag Write to 1 to clear the CCF interrupt flag. Clear Slave-Select In Master Mode Interrupt Flag Write to 1 to clear the SSM interrupt flag.
Page 221 ...the world's most energy friendly microcontrollers Name Reset Access Description PERR Parity Error Interrupt Enable Enable interrupt on parity error (asynchronous mode only). TXUF TX Underflow Interrupt Enable Enable interrupt on TX underflow. TXOF TX Overflow Interrupt Enable Enable interrupt on TX overflow. RXUF RX Underflow Interrupt Enable Enable interrupt on RX underflow.
Page 222 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description No filter enabled Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected IRPW IrDA TX Pulse Width Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period. Value Mode Description...
Page 223 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description The U(S)n_TX (MOSI) pin is disabled The U(S)n_TX (MOSI) pin is enabled RXPEN RX Pin Enable When set, the RX/MISO pin of the USART is enabled. Value Description The U(S)n_RX (MISO) pin is disabled The U(S)n_RX (MISO) pin is enabled 15.5.23 USARTn_INPUT - USART Input Register...
Page 224 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 FORMAT I2S Word Format Configure the data-width used internally for I2S data Value Mode Description...
Page 225: Leuart - Low Energy Universal Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 16 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? The LEUART provides full UART communication using a low frequency 32.768 0 1 2 3 kHz clock, and has special features for communication without CPU intervention. Why? It allows UART communication to be controller...
Page 226: Functional Description
...the world's most energy friendly microcontrollers • Can use a high frequency clock source for even higher baud rates • Configurable number of data bits: 8 or 9 (plus parity bit, if enabled) • Configurable parity: off, even or odd •...
Page 227 ...the world's most energy friendly microcontrollers low for one bit-period. This signals the start of a frame, and is used for synchronization. Following the start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least significant bit first.
Page 228: Leuart Baud Rates
...the world's most energy friendly microcontrollers The clock divider used in the LEUART is a 12-bit value, with a 7-bit integral part and a 5-bit fractional part. The baud rate of the LEUART is given by : LEUART Baud Rate Equation br = fLEUARTn/(1 + LEUARTn_CLKDIV/256) (16.1) where fLEUARTn is the clock frequency supplied to the LEUART.
Page 229 ...the world's most energy friendly microcontrollers If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF is set, indicating the overflow. The data already in the buffer is in that case preserved, and no data is written.
Page 230 ...the world's most energy friendly microcontrollers 16.3.4.3 Jitter in Transmitted Data Internally the LEUART module uses only the positive edges of the 32.768 kHz clock (LFBCLK) for transmission and reception. Transmitted data will thus have jitter equal to the difference between the optimal data set-up location and the closest positive edge on the 32.768 kHz clock.
Page 231 ...the world's most energy friendly microcontrollers Figure 16.4. LEUART Receiver Overview RXDATA RXENS !RXBLOCK Receive shift register LEUn_RX d0- d8 status status Receive buffer RXDATAX (RXDATAXP) 16.3.5.2 Blocking Incoming Data When using hardware frame recognition, as detailed in Section 16.3.5.6 (p. 232) , Section 16.3.5.7 (p. 233) , and Section 16.3.5.8 (p.
Page 232: Leuart Optimal Sampling Point
...the world's most energy friendly microcontrollers LEUART Optimal Sampling Point (n) = n (1 + LEUARTn_CLKDIV/256) + CLKDIV/512 (16.3) where n is the bit-index. Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are performed on the closest positive edge, i.e.
Page 233 ...the world's most energy friendly microcontrollers When 8 data-bit frame formats are used, only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming frames. The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits. Note The receiver must be enabled for start frames to be detected.
Page 234 ...the world's most energy friendly microcontrollers Figure 16.5. LEUART Local Loopback LOOPBK = 0 LOOPBK = 1 µC µC LEUART LEUART LEUn_TX LEUn_TX LEUn_RX LEUn_RX 16.3.7 Half Duplex Communication When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same time.
Page 235 ...the world's most energy friendly microcontrollers 16.3.7.3 Two Data-links Some limited devices only support half duplex communication even though two data links are available. In this case software is responsible for making sure data is not transmitted when incoming data is expected.
Page 236 ...the world's most energy friendly microcontrollers EM2/EM3 before the frame has been read from the LEUART. In order for the system to go to EM2 during the last byte transmission, LEUART_CTRL_TXDMAWU must be cleared in the DMA interrupt service routine. This is because TXBL will be high during that last byte transfer.
Page 237: Register Map
...the world's most energy friendly microcontrollers 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LEUARTn_CTRL Control Register 0x004 LEUARTn_CMD Command Register 0x008 LEUARTn_STATUS Status Register 0x00C LEUARTn_CLKDIV Clock Control Register 0x010 LEUARTn_STARTFRAME Start Frame Register...
Page 238 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description TRIPLE Transmission of new frames are delayed by three baud periods TXDMAWU TX DMA Wakeup Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer. Value Description While in EM2, the DMA controller will not get requests about space being available in the transmit buffer...
Page 239 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description One stop-bit is transmitted with every frame Two stop-bits are transmitted with every frame PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used. Value Mode Description...
Page 240 ...the world's most energy friendly microcontrollers Name Reset Access Description RXDIS Receiver Disable Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded. RXEN Receiver Enable Set to activate data reception on LEUn_RX. 16.5.3 LEUARTn_STATUS - Status Register Offset Bit Position...
Page 241 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 14:3 0x000 Fractional Clock Divider Specifies the fractional clock divider for the LEUART. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 242 ...the world's most energy friendly microcontrollers 16.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERR Receive Data Framing Error Set if data in buffer has a framing error.
Page 243 ...the world's most energy friendly microcontrollers 16.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERRP Receive Data Framing Error Peek Set if data in buffer has a framing error.
Page 244 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description The transmitter is disabled, clearing TXENS after the frame has been transmitted TXBREAK Transmit Data As Break Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.
Page 245 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when a multi-processor address frame is detected. FERR Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cleared. PERR Parity Error Interrupt Flag Set when a frame with a parity error is received while RXBLOCK is cleared.
Page 246 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to set the RXOF interrupt flag. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Set TX Complete Interrupt Flag Write to 1 to set the TXC interrupt flag.
Page 247 ...the world's most energy friendly microcontrollers 16.5.15 LEUARTn_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SIGF Signal Frame Interrupt Enable Enable interrupt on signal frame.
Page 248 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PULSEFILT Pulse Filter Enable a one-cycle pulse filter for pulse extender Value Description Filter is disabled.
Page 249 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to TXDATA is being synchronized. TXDATAX TXDATAX Register Busy Set when the value written to TXDATAX is being synchronized. SIGFRAME SIGFRAME Register Busy Set when the value written to SIGFRAME is being synchronized. STARTFRAME STARTFRAME Register Busy Set when the value written to STARTFRAME is being synchronized.
Page 250 ...the world's most energy friendly microcontrollers 16.5.20 LEUARTn_INPUT - LEUART Input Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXPRS PRS RX Enable When set, the PRS channel selected as input to RX.
Page 251: Timer - Timer/Counter
...the world's most energy friendly microcontrollers 17 TIMER - Timer/Counter Quick Facts What? 0 1 2 3 The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms and triggers timed actions in other peripherals. USART Why? Most applications have activities that need to be timed accurately with as little CPU intervention and energy consumption as TIMER...
Page 252: Functional Description
...the world's most energy friendly microcontrollers • Two capture registers for each capture channel • Capture on either positive or negative edge • Capture on both edges • Optional digital noise filtering on capture inputs • Output Compare • Compare output toggle/pulse on compare match •...
Page 253 ...the world's most energy friendly microcontrollers 1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again. 2. Down-count: The counter starts at the value in TIMERn_TOP and counts down. When it reaches 0, it is reloaded with the value in TIMERn_TOP.
Page 254 ...the world's most energy friendly microcontrollers Figure 17.2. TIMER Hardware Timer/Counter Control Counter RISEA FALLA (Controlled by TIMERn_CTRL) Start Counter Stop Reload&Start Compare/ Capture channel 0 (Controlled by TIMERn_CC0_CTRL) INSEL ICEDGE TIMn_CC0 Input PRS channels Capture 0 Filter PRSSEL FILT 17.3.1.3 Clock Source The counter can be clocked from several sources, which are all synchronized with the peripheral clock (HFPERCLK).
Page 255 ...the world's most energy friendly microcontrollers 17.3.1.3.3 Underflow/Overflow from Neighboring Timer All Timers are linked together (see Figure 17.4 (p. 255) ), allowing timers to count on overflow/underflow from the lower numbered neighbouring timers to form a 32-bit or 48-bit timer. Note that all timers must be set to same count direction and less significant timer(s) can only be set to count up or down.
Page 256: Timer Quadrature Encoded Inputs
...the world's most energy friendly microcontrollers Figure 17.6. TIMER Quadrature Encoded Inputs Channel A ° Channel B Forward rotation (Channel A leads Channel B) Channel A Channel B ° Backward rotation (Channel B leads Channel A) In the Timer these inputs are tapped from the Compare/Capture channel 0 (Channel A) and 1 (Channel B) inputs before edge detection.
Page 257: Timer Counter Response In X2 Decoding Mode
...the world's most energy friendly microcontrollers Table 17.1. TIMER Counter Response in X2 Decoding Mode Channel A Channel B Rising Falling Increment Decrement Decrement Increment Figure 17.8. TIMER X2 Decoding Mode Channel A Channel B 17.3.1.6.2 X4 Decoding Mode In X4 Decoding mode, the counter increments or decrements on every edge of Channel A and Channel B, see Figure 17.9 (p.
Page 258 ...the world's most energy friendly microcontrollers 1. Input Capture 2. Output Compare 3. PWM 17.3.2.1 Input Pin Logic Each Compare/Capture channel can be configured as an input source for the Capture Unit or as external clock source for the Timer (see Figure 17.10 (p. 258) ). Compare/Capture channels 0 and 1 are the inputs for the Quadrature Decoder Mode.
Page 259: Timer Input Capture Buffer Functionality
...the world's most energy friendly microcontrollers Figure 17.11. TIMER Input Capture Buffer Functionality CCVB FIFO 17.3.2.2.2 Compare and PWM Mode When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
Page 260: Timer Input Capture
...the world's most energy friendly microcontrollers Figure 17.13. TIMER Input Capture Input TIMERn_CNT TIMERn_CCx _CCV prev. val prev. val TIMERn_CCx _CCVB Read TIMERn_CCx _CCVB 17.3.2.3.1 Period/Pulse-Width Capture Period and/or pulse-width capture can be achieved by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either external pin or PRS, see Figure 17.14 (p.
Page 261 ...the world's most energy friendly microcontrollers Figure 17.15. TIMER Block Diagram Showing Comparison Functionality Update Condition CNTCLK TIMERn_CNT TIMERn_TOP Overflow Underflow Note: For sim plicity, all TIMERn_CCx registers are grouped together in the figure, Com pare Match x but they all have individual Com pare Register and logic Com pare and TnCCR1[15:0...
Page 262: Timer Up-Count Frequency Generation
...the world's most energy friendly microcontrollers Figure 17.17. TIMER Up-count Frequency Generation TIMERn_TOP TIMERn_CCx _CCV The output frequency is given by Equation 17.2 (p. 262) TIMER Up-count Frequency Generation Equation / ( 2^(PRESC + 1) x (TOP + 1) x 2) (17.2) HFPERCLK 17.3.2.5 Pulse-Width Modulation (PWM)
Page 263: Timer Cc Out In 2X Mode
...the world's most energy friendly microcontrollers TIMER Up-count Duty Cycle Equation = CCVx/TOP (17.5) 17.3.2.6.1 2x Count Mode When the Timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number.
Page 264: Timer Up/Down-Count Pwm Generation
...the world's most energy friendly microcontrollers Figure 17.20. TIMER Up/Down-count PWM Generation TIMERn_TOP TIMERn_CCx _CCV TIMn_CCx Overflow Com pare m atch Buffer update TIMER Up/Down-count PWM Resolution Equation = log(TOP+1)/log(2) (17.9) up/down The PWM frequency is given by Equation 17.10 (p. 264) : TIMER Up/Down-count PWM Frequency Equation / ( 2^(PRESC+1) x TOP) (17.10)
Page 265: Timer Events
...the world's most energy friendly microcontrollers = log(TOP/2+1)/log(2) (17.12) 2xmode The PWM frequency is given by Equation 17.7 (p. 263) : TIMER 2x Mode PWM Frequency Equation( Up/Down-count) / TOP (17.13) HFPERCLK 2xmode The high duty cycle is given by Equation 17.14 (p. 265) TIMER 2x Mode Duty Cycle Equation = CCVx/TOP (17.14)
Page 266: Register Map
...the world's most energy friendly microcontrollers 17.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IEN Interrupt Enable Register 0x010 TIMERn_IF Interrupt Flag Register...
Page 267: Register Description
...the world's most energy friendly microcontrollers 17.5 Register Description 17.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RSSCOIST Reload-Start Sets Compare Ouptut initial State When enabled, compare output is set to COIST value at Reload-Start event...
Page 268 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description STOP Stop counter without reload RELOADSTART Reload and start counter RISEA Timer Rising Input Edge Action These bits select the action taken in the counter when a rising edge occurs on the input. Value Mode Description...
Page 269 ...the world's most energy friendly microcontrollers 17.5.2 TIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) STOP Stop Timer Write a 1 to this bit to stop timer...
Page 270 ...the world's most energy friendly microcontrollers Name Reset Access Description 23:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICV2 CC2 Input Capture Valid This bit indicates that TIMERn_CC2_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off).
Page 271 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DOWN Counting down RUNNING Running Indicates if timer is running or not. 17.5.4 TIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:11...
Page 272 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICBOF2 CC Channel 2 Input Capture Buffer Overflow Interrupt Flag This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC2_CCV/TIMERn_CC2_CCVB register pair.
Page 273 ...the world's most energy friendly microcontrollers Name Reset Access Description Writing a 1 to this bit will set Compare/Capture channel 1 interrupt flag. CC Channel 0 Interrupt Flag Set Writing a 1 to this bit will set Compare/Capture channel 0 interrupt flag. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 274 ...the world's most energy friendly microcontrollers 17.5.8 TIMERn_TOP - Counter Top Value Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0xFFFF Counter Top Value...
Page 275 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 Counter Value These bits hold the counter value. 17.5.11 TIMERn_ROUTE - I/O Routing Register Offset Bit Position...
Page 276 ...the world's most energy friendly microcontrollers 17.5.12 TIMERn_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:26 ICEVCTRL Input Capture Event Control...
Page 277 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRSCH7 PRS Channel 7 selected as input 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 13:12 CUFOA Counter Underflow Output Action...
Page 278 ...the world's most energy friendly microcontrollers 17.5.13 TIMERn_CCx_CCV - CC Channel Value Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 CC Channel Value...
Page 279 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 CCVB 0x0000 CC Channel Value Buffer In Input Capture mode, this field holds the last capture value if the TIMERn_CCx_CCV register already contains an earlier unread capture value.
Page 280 ...the world's most energy friendly microcontrollers 17.5.17 TIMERn_DTTIME - DTI Time Control Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:16 DTFALLT 0x00...
Page 281 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTLOCKUPFEN DTI Lockup Fault Enable Set this bit to 1 to enable core lockup as a fault source DTDBGFEN DTI Debugger Fault Enable Set this bit to 1 to enable debugger as a fault source...
Page 282 ...the world's most energy friendly microcontrollers 17.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTOGCDTI2EN DTI CDTI2 Output Generation Enable This bit enables/disables output generation for the CDTI2 output from the DTI.
Page 283 ...the world's most energy friendly microcontrollers Name Reset Access Description DTPRS0F DTI PRS 0 Fault This bit is set to 1 if a PRS 0 fault has occurred and DTPRS0FEN is set to 1. The TIMER0_DTFAULTC register can be used to clear fault bits.
Page 284 ...the world's most energy friendly microcontrollers Name Reset Access Description Mode Value Description Write Operation LOCK Lock TIMER DTI registers UNLOCK 0xCE80 Unlock TIMER DTI registers www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 285: Rtc - Real Time Counter
...the world's most energy friendly microcontrollers 18 RTC - Real Time Counter Quick Facts What? The Real Time Counter (RTC) ensures timekeeping in low energy modes. Combined with two low power oscillators (XTAL or RC), the RTC can run in EM2 with total current consumption less than 1.0 µA, and in EM3 0 1 2 3 with total current consumption less than 0.6...
Page 286: Functional Description
...the world's most energy friendly microcontrollers 18.3 Functional Description The RTC is a 24-bit counter with two compare channels. The RTC is closely coupled with the LETIMER, and can be configured to trigger it on a compare match on one or both compare channels. An overview of the RTC module is shown in Figure 18.1 (p.
Page 287 ...the world's most energy friendly microcontrollers Table 18.1. RTC Resolution Vs Overflow RTC_PRESC Resolution Overflow 30,5 µs 512 s 61,0 µs 1024 s 122 µs 2048 s 244 µs 1,14 hours 488 µs 2,28 hours 977 µs 4,55 hours 1,95 ms 9,10 hours 3,91 ms 18,2 hours...
Page 288 ...the world's most energy friendly microcontrollers 18.3.4 Debugrun By default, the RTC is halted when code execution is halted from the debugger. By setting the DEBUGRUN bit in the RTC_CTRL register, the RTC will continue to run even when the debugger is halted.
Page 289: Register Map
...the world's most energy friendly microcontrollers 18.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTC_CTRL Control Register 0x004 RTC_CNT Counter Value Register 0x008 RTC_COMP0 Compare Value Register 0 0x00C RTC_COMP1 Compare Value Register 1 0x010...
Page 290 ...the world's most energy friendly microcontrollers 18.5.2 RTC_CNT - Counter Value Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 0x000000 Counter Value...
Page 291 ...the world's most energy friendly microcontrollers Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 COMP1 0x000000 Compare Value 1 A compare match event occurs when CNT is equal to this value.
Page 292 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) COMP1 Set Compare match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag.
Page 293 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable interrupt on overflow. 18.5.9 RTC_FREEZE - Freeze Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the RTC is postponed until this bit is cleared.
Page 294: Letimer - Low Energy Timer
...the world's most energy friendly microcontrollers 19 LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32.768 Hz clock the LETIMER is available in EM2, while 0 1 2 3 using a 1 kHz clock the LETIMER is available also in EM3, all this with sub µA current...
Page 295: Functional Description
...the world's most energy friendly microcontrollers • Interrupt on: • Compare matches • Timer underflow • Repeat done • Optionally runs during debug • PRS Output 19.3 Functional Description An overview of the LETIMER module is shown in Figure 19.1 (p. 295) . The LETIMER is a 16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1.
Page 296 ...the world's most energy friendly microcontrollers 19.3.2 Compare Registers The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1. Each of these compare registers are capable of generating an interrupt when the counter value LETIMERn_CNT becomes equal to their value. When LETIMERn_CNT becomes equal to the value of LETIMERn_COMP0, the interrupt flag COMP0 in LETIMERn_IF is set, and when LETIMERn_CNT becomes equal to the value of LETIMERn_COMP1, the interrupt flag COMP1 in LETIMERn_IF is set.
Page 297 ...the world's most energy friendly microcontrollers 19.3.3.2.1 Free Mode In the free running mode, the LETIMER acts as a regular timer, and the repeat counter is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in Figure 19.2 (p.
Page 298 ...the world's most energy friendly microcontrollers Figure 19.3. LETIMER One-shot Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 RUNNING Else if (START) RUNNING = 1 End if START START = 0 STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 299 ...the world's most energy friendly microcontrollers Figure 19.4. LETIMER Buffered Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 300: Letimer Clock Frequency
...the world's most energy friendly microcontrollers Figure 19.5. LETIMER Double Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 301 ...the world's most energy friendly microcontrollers continue running if triggered while it is running, so the multiple-triggering will only have an effect if you try to disable the RTC when it is being triggered. 19.3.3.5 Debug If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the CPU is halted during a debug session, and resumes operation when the CPU continues.
Page 302 ...the world's most energy friendly microcontrollers Some simple waveforms generated with the different output modes are shown in Figure 19.6 (p. 302) . For the example, REPMODE in LETIMERn_CTRL has been cleared, COMP0TOP also in LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to 3. As seen in the figure, LETIMERn_COMP0 now decides the length of the signal periods.
Page 303 ...the world's most energy friendly microcontrollers Figure 19.8. LETIMER Dual Output UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 19.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system.
Page 304: Letimer Triggered Operation
...the world's most energy friendly microcontrollers 19.3.6.1 Triggered Output Generation Example 19.1. LETIMER Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started.
Page 305: Letimer Continuous Operation
...the world's most energy friendly microcontrollers 19.3.6.2 Continuous Output Generation Example 19.2. LETIMER Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 19.6 (p. 302) , but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
Page 306 ...the world's most energy friendly microcontrollers Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 19.10 (p. 305) assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 19.11 (p.
Page 307 ...the world's most energy friendly microcontrollers 19.3.7 Using the LETIMER in EM3 The LETIMER can be enabled all the way down to EM3 by using the ULFRCO as clock source. This is done by clearing CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1. This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator (ULFRCO), consuming very little energy.
Page 308: Register Map
...the world's most energy friendly microcontrollers 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL Control Register 0x004 LETIMERn_CMD Command Register 0x008 LETIMERn_STATUS Status Register 0x00C LETIMERn_CNT Counter Value Register 0x010 LETIMERn_COMP0 Compare Value Register 0...
Page 309 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description A compare match on RTC compare channel 1 starts the LETIMER if the LETIMER is not already started RTCC0TEN RTC Compare 0 Trigger Enable Allows the LETIMER to be started on a compare match on RTC compare channel 0. Value Description LETIMER is not affected by RTC compare channel 0...
Page 310 ...the world's most energy friendly microcontrollers 19.5.2 LETIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CTO1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value...
Page 311 ...the world's most energy friendly microcontrollers 19.5.4 LETIMERn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 Counter Value...
Page 312 ...the world's most energy friendly microcontrollers Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 COMP1 0x0000 Compare Value 1 Compare and optionally buffered top value for LETIMER 19.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
Page 313 ...the world's most energy friendly microcontrollers Name Reset Access Description REP1 0x00 Repeat Counter 1 Optional repeat counter or buffer for REP0 19.5.9 LETIMERn_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 314 ...the world's most energy friendly microcontrollers Name Reset Access Description COMP1 Set Compare Match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare Match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag. 19.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 315 ...the world's most energy friendly microcontrollers Name Reset Access Description Underflow Interrupt Enable Set to enable interrupt on the UF interrupt flag. COMP1 Compare Match 1 Interrupt Enable Set to enable interrupt on the COMP1 interrupt flag. COMP0 Compare Match 0 Interrupt Enable Set to enable interrupt on the COMP0 interrupt flag.
Page 316 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to COMP0 is being synchronized. CMD Register Busy Set when the value written to CMD is being synchronized. CTRL CTRL Register Busy Set when the value written to CTRL is being synchronized. 19.5.15 LETIMERn_ROUTE - I/O Routing Register Offset Bit Position...
Page 317: Pcnt - Pulse Counter
...the world's most energy friendly microcontrollers 20 PCNT - Pulse Counter Quick Facts What? 0 1 2 3 The Pulse Counter (PCNT) decodes incoming pulses. The module has a quadrature mode which may be used to decode the speed and direction of a mechanical shaft.
Page 318: Pcnt Overview
...the world's most energy friendly microcontrollers Figure 20.1. PCNT Overview CMU (conseptual) LFACLK Clock switch PCNT S0PRS Input Peripheral bus OVR_SINGLE Edge Pulse Width Inverter detector Filter TOPB EXTCLK_SINGLE EXTCLK_QUAD Quadrature Inverter decoder S1PRS Input 20.3.1 Pulse Counter Modes The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode (EXTCLKQUAD).
Page 319 ...the world's most energy friendly microcontrollers The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads is capable of removing some unwanted noise. However, this mode may be susceptible to spikes and unintended pulses from devices such as mechanical switches, and is therefore most suited to take input from electronic sensors etc.
Page 320: Absolute Position With Hysteresis And Even Top Value
...the world's most energy friendly microcontrollers The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by Table 20.1 (p. 320) . Note that this function also filters some invalid inputs that may occur when the shaft changes direction or temporarily toggles direction.
Page 321 ...the world's most energy friendly microcontrollers As the auxiliary counter, the main counter can be configured to count only on certain events. This is done through CNTEV in PCNTn_CTRL, and it is possible like for the auxiliary counter, to make the main counter count on only up and down events.
Page 322 ...the world's most energy friendly microcontrollers In EXTCLKQUAD mode, the EDGE bit in PCNTn_CTRL inverts the direction of the counter (which is automatically detected). Note The EDGE bit in PCNTn_CTRL has no effect in EXTCLKSINGLE mode. 20.3.8 PRS S0IN and S1IN Input It is possible to receive input from PRS on both SOIN and S1IN by setting S0PRSEN or S1PRSEN in PCNTn_INPUT.
Page 323: Register Map
...the world's most energy friendly microcontrollers 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register 0x010 PCNTn_TOP Top Value Register...
Page 324 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description BOTH Counts up on up-count and down on down-count events. Only counts up on up-count events. DOWN Only counts down on down-count events. NONE Never counts. S1CDIR Count direction determined by S1 S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes.
Page 325 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LTOPBIM Load TOPB Immediately This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. LCNTIM Load CNT Immediately Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
Page 326 ...the world's most energy friendly microcontrollers 20.5.5 PCNTn_TOP - Top Value Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x00FF Counter Top Value...
Page 327 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) AUXOF Overflow Interrupt Read Flag Set when an Auxiliary CNT overflow occurs DIRCNG Direction Change Detect Interrupt Flag Set when the count direction changes.
Page 328 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear the auxiliary overflow interrupt flag DIRCNG Direction Change Detect Interrupt Clear Write to 1 to clear the direction change detect interrupt flag Overflow Interrupt Clear Write to 1 to clear the overflow interrupt flag Underflow Interrupt Clear Write to 1 to clear the underflow interrupt flag...
Page 329 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20.5.12 PCNTn_FREEZE - Freeze Register Offset Bit Position...
Page 330 ...the world's most energy friendly microcontrollers 20.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 AUXCNT 0x0000...
Page 331 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) S0PRSSEL S0IN PRS Channel Select Select PRS channel as input to S0IN. Value Mode Description...
Page 332: Lesense - Low Energy Sensor Interface
Why? Capability to autonomously monitor sensors allows the EFM32TG to reside in a low energy mode for long periods of time while keeping track of sensor status and sensor events.
Page 333: Functional Description
...the world's most energy friendly microcontrollers 21.3 Functional description LESENSE is a module capable of controlling on-chip peripherals in order to perform monitoring of different sensors with little or no CPU intervention. LESENSE uses the analog comparators, ACMP, for measurement of sensor signals. LESENSE can also control the DAC to generate accurate reference voltages.
Page 334 ...the world's most energy friendly microcontrollers the channel configuration registers, CHx_TIMING, CHx_INTERACT, and CHx_EVAL, throughout this chapter. By default, the channel configuration registers are directly mapped to the channel number. Configuring SCANCONF in CTRL makes it possible to alter this mapping. Configuring SCANCONF to INVMAP will make channels 0-7 use the channel configuration registers for channels 8-15, and vice versa.
Page 335: Scan Sequence
...the world's most energy friendly microcontrollers ONESHOT, a single scan will be made when START in CMD is set. To start a new scan on a PRS event, set START in CMD, set SCANMODE to PRS and configure PRS channel in PRSSEL. The PRS start signal needs to be active for at least one LFACLK cycle to make sure LESENSE is able LESENSE...
Page 336 ...the world's most energy friendly microcontrollers 21.3.4 Sensor interaction Many sensor types require some type of excitation in order to work. LESENSE can generate a variety of sensor stimuli, both on the same pin as the measurement is to be made on, and on alternative pins. By default, excitation is performed on the pin associated with the channel, i.e.
Page 337: Pin Sequencing
...the world's most energy friendly microcontrollers Figure 21.4 (p. 337) illustrates the sequencing of the pin associated with the active channel and its alternative excite pin. Figure 21.4. Pin sequencing LFACLK LESENSE EXCITE Idle phase Ex cite phase Measure phase Idle phase Channel pin IDLECONF...
Page 338 ...the world's most energy friendly microcontrollers Figure 21.5. Scan result and interrupt generation CHx _EVAL_SCANRESINV ACMP ACMP sam ple SCANRES[x ] NEGEDGE COUNTER > = COMPTHRES POSEDGE interrupt LESENSE flag COUNTER counter LEVEL CHx _INTERACT_SAMPLE SENSORSTATE NONE COUNTER < COMPTHRES LESS CHx _EVAL_COMP CHx _INTERACT_SETIF...
Page 339 1 being up and 0 being down. The count direction will be kept at its previous state in between count events. The EFM32TG pulse counter may be used to keep track of events based on these PRS outputs.
Page 340 ...the world's most energy friendly microcontrollers Figure 21.7. Decoder state transition evaluation STATE TCONF Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE CHAIN _TCONF...
Page 341 ...the world's most energy friendly microcontrollers Figure 21.8. Decoder hysteresis State 0 A transition: Transition defined in TCONFA B transition: Transition defined in TCONFB 1: B transition, no hysteresis State 1 2: A transition, hysteresis 4: A transition, hysteresis 3: B transition, hysteresis State 2 5: A transition, no hysteresis State 3...
Page 342: Bias Configuration
The prescaler may also be used to tune how long the DAC should drive its outputs in sample/off mode. Bias configuration, calibration and reference selection is done in the EFM32TG DAC module and LESENSE will not override these configurations. If a bandgap reference is selected for the DAC, the DACREF bit in PERCTRL should be set to BANDGAP.
Page 343 Note Read-modify-write operations on uninitialized RAM register produces undefined values. 21.3.14 Application examples 21.3.14.1 Capacitive sense Figure 21.10 (p. 344) illustrates how the EFM32TG can be configured to monitor four capacitive buttons. www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 344: Capacitive Sense Setup
To enable storing of the count value for a channel, set STRSAMPLE in the CHx_INTERACT register. 21.3.14.2 LC sensor Figure 21.11 (p. 344) below illustrates how the EFM32TG can be set up to monitor four LC sensors. Figure 21.11. LC sensor setup EFM32...
Page 345 ...the world's most energy friendly microcontrollers exceeds a certain level. These pulses are counted using an asynchronous counter and compared with the threshold in COMPTHRES in the CHx_EVAL register. If the number of pulses exceeds the threshold level, the sensor is said to be active, otherwise it is inactive. Figure 21.12 (p. 345) illustrates how the output pulses from the ACMP correspond to damping of the oscillations.
Page 346 ...the world's most energy friendly microcontrollers Figure 21.13. FSM example 1 Sensor value State Index 010 110 000 100 To set up the decoder to decode rotation using the encoding scheme seen in Figure 21.13 (p. 346) , configure the following LESENSE registers: 1.
Page 347: Lesense Decoder Configuration
...the world's most energy friendly microcontrollers 1. Configure STx_TCONFA and STx_TCONFB as described in Table 21.4 (p. 347) . Table 21.4. LESENSE decoder configuration Register NEXTSTATE COMP MASK CHAIN ST0_TCONFA 0b1000 0b0111 ST0_TCONFB 0b0001 0b1000 ST1_TCONFA 0b0010 0b1000 ST1_TCONFB 0b0010 0b1000 ST2_TCONFA 0b1000...
Page 348: Register Map
...the world's most energy friendly microcontrollers 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LESENSE_CTRL Control Register 0x004 LESENSE_TIMCTRL Timing Control Register 0x008 LESENSE_PERCTRL Peripheral Control Register 0x00C LESENSE_DECCTRL Decoder control Register 0x010 LESENSE_BIASCTRL...
Page 349: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x3B8 LESENSE_CH15_EVAL Scan configuration 21.5 Register Description 21.5.1 LESENSE_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x000 Reset Access...
Page 350 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ALTEX Alternative excitation is mapped to the LES_ALTEX pins. ACMP Alternative excitation is mapped to the pins of the other ACMP. ACMP1INV Invert analog comparator 1 output ACMP0INV Invert analog comparator 0 output Reserved...
Page 351 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:22 STARTDLY Start delay configuration Delay sensor interaction STARTDELAY LFACLK cycles for each channel LESENSE 21:20...
Page 352 ...the world's most energy friendly microcontrollers Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:26 WARMUPMODE ACMP and DAC duty cycle mode Value Mode Description...
Page 353 ...the world's most energy friendly microcontrollers Name Reset Access Description DACCH0OUT DAC channel 0 output mode Value Mode Description DISABLE DAC CH0 output to pin and ACMP/ADC disabled DAC CH0 output to pin enabled, output to ADC and ACMP disabled ADCACMP DAC CH0 output to pin disabled, output to ADC and ACMP enabled PINADCACMP...
Page 354 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRSCH0 PRS Channel 0 selected as input PRSCH1 PRS Channel 1 selected as input PRSCH2 PRS Channel 2 selected as input PRSCH3 PRS Channel 3 selected as input PRSCH4 PRS Channel 4 selected as input PRSCH5...
Page 355 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRS channels are used as input to the decoder. PRSCNT Enable count mode on decoder PRS channels 0 and 1 When set, decoder PRS0 and PRS1 will be used to produce output which can be used by a PCNT to count up or down. HYSTIRQ Enable decoder hysteresis on interrupt requests When set, hysteresis is enabled in the decoder, suppressing interrupt requests.
Page 356 ...the world's most energy friendly microcontrollers 21.5.6 LESENSE_CMD - Command Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLEARBUF Clear result buffer DECODE...
Page 357 ...the world's most energy friendly microcontrollers Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 SCANRES 0x0000 Scan results Bit X will be set depending on channel X evaluation 21.5.9 LESENSE_STATUS - Status Register (Async Reg)
Page 358 ...the world's most energy friendly microcontrollers Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Result buffer write pointer. These bits show the next index in the result buffer to be written to.
Page 359 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CURCH Shows the index of the current channel 21.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 360 ...the world's most energy friendly microcontrollers Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:30 CH15 Channel 15 idle phase configuration Value Mode Description DISABLE CH15 output is disabled in idle phase HIGH CH15 output is high in idle phase CH15 output is low in idle phase DACCH1 CH15 output is connected to DAC CH1 output in idle phase...
Page 361 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DISABLE CH9 output is disabled in idle phase HIGH CH9 output is high in idle phase CH9 output is low in idle phase 17:16 Channel 8 idle phase configuration Value Mode Description...
Page 362 ...the world's most energy friendly microcontrollers Name Reset Access Description Channel 1 idle phase configuration Value Mode Description DISABLE CH1 output is disabled in idle phase HIGH CH1 output is high in idle phase CH1 output is low in idle phase DACCH0 CH1 output is connected to DAC CH0 output in idle phase Channel 0 idle phase configuration...
Page 363 ...the world's most energy friendly microcontrollers Name Reset Access Description 15:14 IDLECONF7 ALTEX7 idle phase configuration Value Mode Description DISABLE ALTEX7 output is disabled in idle phase HIGH ALTEX7 output is high in idle phase ALTEX7 output is low in idle phase 13:12 IDLECONF6 ALTEX6 idle phase configuration...
Page 364 ...the world's most energy friendly microcontrollers 21.5.17 LESENSE_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CNTOF Set when the LESENSE counter overflows.
Page 365 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when channel 6 triggers Set when channel 5 triggers Set when channel 4 triggers Set when channel 3 triggers Set when channel 2 triggers Set when channel 1 triggers Set when channel 0 triggers 21.5.18 LESENSE_IFC - Interrupt Flag Clear Register Offset...
Page 366 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear CH14 interrupt flag CH13 Write to 1 to clear CH13 interrupt flag CH12 Write to 1 to clear CH12 interrupt flag CH11 Write to 1 to clear CH11 interrupt flag CH10 Write to 1 to clear CH10 interrupt flag Write to 1 to clear CH9 interrupt flag...
Page 367 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to set the CNTOF interrupt flag BUFOF Write to 1 to set the BUFOF interrupt flag BUFLEVEL Write to 1 to set the BUFLEVEL interrupt flag BUFDATAV Write to 1 to set the BUFDATAV interrupt flag DECERR Write to 1 to set the DECERR interrupt flag...
Page 368 ...the world's most energy friendly microcontrollers 21.5.20 LESENSE_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CNTOF Set to enable interrupt on the CNTOF interrupt flag BUFOF...
Page 369 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to enable interrupt on the CH5 interrupt flag Set to enable interrupt on the CH4 interrupt flag Set to enable interrupt on the CH3 interrupt flag Set to enable interrupt on the CH2 interrupt flag Set to enable interrupt on the CH1 interrupt flag Set to enable interrupt on the CH0 interrupt flag 21.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register...
Page 370 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to LESENSE_IDLECONF is being synchronized. SENSORSTATE LESENSE_SENSORSTATE Register Busy Set when the value written to LESENSE_SENSORSTATE is being synchronized. DECSTATE LESENSE_DECSTATE Register Busy Set when the value written to LESENSE_DECSTATE is being synchronized. CURCH LESENSE_CURCH Register Busy Set when the value written to LESENSE_CURCH is being synchronized.
Page 371 ...the world's most energy friendly microcontrollers Name Reset Access Description ALTEX6PEN ALTEX6 Pin Enable ALTEX5PEN ALTEX5 Pin Enable ALTEX4PEN ALTEX4 Pin Enable ALTEX3PEN ALTEX3 Pin Enable ALTEX2PEN ALTEX2 Pin Enable ALTEX1PEN ALTEX1 Pin Enable ALTEX0PEN ALTEX0 Pin Enable CH15PEN CH15 Pin Enable CH14PEN CH14 Pin Enable CH13PEN...
Page 372 ...the world's most energy friendly microcontrollers Name Reset Access Description 21.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x058 Reset Access Name Name Reset Access Description...
Page 373 ...the world's most energy friendly microcontrollers Name Reset Access Description DECCTRL_PRSCNT = 0 PRS1 Generate pulse on LESPRS1 PRS01 Generate pulse on LESPRS0 and LESPRS1 PRS2 Generate pulse on LESPRS2 PRS02 Generate pulse on LESPRS0 and LESPRS2 PRS12 Generate pulse on LESPRS1 and LESPRS2 PRS012 Generate pulse on LESPRS0, LESPRS1 and LESPRS2 DECCTRL_PRSCNT = 1...
Page 374 ...the world's most energy friendly microcontrollers Name Reset Access Description DECCTRL_PRSCNT = 0 PRS12 Generate pulse on PRS1 and PRS2 PRS012 Generate pulse on PRS0, PRS1 and PRS2 DECCTRL_PRSCNT = 1 NONE Do not count Count up DOWN Count down PRS2 Generate pulse on PRS2 UPANDPRS2...
Page 375 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:13 MEASUREDLY 0xXX Set measure delay Configure measure delay. Sensor measuring is delayed for MEASUREDLY+1 EXCLK cycles. 12:6 SAMPLEDLY 0xXX...
Page 376 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LEVEL Set interrupt flag if the sensor triggers. POSEDGE Set interrupt flag on positive edge on the sensor state NEGEDGE Set interrupt flag on negative edge on the sensor state SAMPLE Select sample mode Select if ACMP output or counter output should be used in comparison...
Page 377 ...the world's most energy friendly microcontrollers www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 378: Acmp - Analog Comparator
...the world's most energy friendly microcontrollers 22 ACMP - Analog Comparator Quick Facts What? The ACMP (Analog Comparator) compares two analog signals and returns a digital value telling which is greater. 0 1 2 3 Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a certain threshold.
Page 379: Functional Description
...the world's most energy friendly microcontrollers • Configurable inversion of comparator output • Configurable output when inactive • Comparator output direct on PRS • Comparator output on GPIO through alternate functionality • Output inversion available 22.3 Functional Description An overview of the ACMP is shown in Figure 22.1 (p. 379) . Figure 22.1.
Page 380 ...the world's most energy friendly microcontrollers One should wait until the warm-up period is over before entering EM2 or EM3, otherwise no comparator interrupts will be detected. EM1 can still be entered during warm-up. After the warm-up period is completed, interrupts will be detected in EM2 and EM3. 22.3.2 Response Time There is a delay from when the actual input voltage changes polarity, to when the output toggles.
Page 381 ...the world's most energy friendly microcontrollers Figure 22.2. 20 mV Hysteresis Selected + 20m V Tim e - 20m V ACMPOUT without hysteresis ACMPOUT with hysteresis 22.3.4 Input Selection The POSSEL and NEGSEL fields in ACMPn_INPUTSEL controls which signals are connected to the two inputs of the comparator.
Page 382: Capacitive Sensing Set-Up
...the world's most energy friendly microcontrollers Figure 22.3. Capacitive Sensing Set-up Buttons POSSEL DD_SCALED 22.3.6 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output, respectively.
Page 383: Register Map
...the world's most energy friendly microcontrollers 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ACMPn_CTRL Control Register 0x004 ACMPn_INPUTSEL Input Selection Register 0x008 ACMPn_STATUS Status Register 0x00C ACMPn_IEN Interrupt Enable Register 0x010 ACMPn_IF Interrupt Flag Register...
Page 384 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 4CYCLES 4 HFPERCLK cycles. 8CYCLES 8 HFPERCLK cycles. 16CYCLES 16 HFPERCLK cycles. 32CYCLES 32 HFPERCLK cycles. 64CYCLES 64 HFPERCLK cycles. 128CYCLES 128 HFPERCLK cycles. 256CYCLES 256 HFPERCLK cycles. 512CYCLES 512 HFPERCLK cycles.
Page 385 ...the world's most energy friendly microcontrollers Name Reset Access Description 29:28 CSRESSEL Capacitive Sense Mode Internal Resistor Select These bits select the resistance value for the internal capacitive sense resistor. Resulting actual resistor values are given in the device datasheets. Value Mode Description...
Page 386 ...the world's most energy friendly microcontrollers 22.5.3 ACMPn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ACMPOUT Analog Comparator Output Analog comparator output value.
Page 387 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Indicates that the analog comparator warm-up period is finished. EDGE Edge Triggered Interrupt Flag Indicates that there has been a rising or falling edge on the analog comparator output.
Page 388 ...the world's most energy friendly microcontrollers 22.5.8 ACMPn_ROUTE - I/O Routing Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 LOCATION I/O Location...
Page 389: Vcmp - Voltage Comparator
...the world's most energy friendly microcontrollers 23 VCMP - Voltage Comparator Quick Facts What? 0 1 2 3 The Voltage Supply Comparator (VCMP) monitors the input voltage supply and generates software interrupts on events using as little as 100 nA. Why? The VCMP can be used for simple power supply monitoring, e.g.
Page 390: Functional Description
...the world's most energy friendly microcontrollers 23.3 Functional Description An overview of the VCMP is shown in Figure 23.1 (p. 390) . Figure 23.1. VCMP Overview Warm up interrupt Warm - up TRIGLEVEL VCMPACT counter Edge interrupt Scaler VCMPOUT INACTVAL BIASPROG HALFBIAS LPREF...
Page 391: Dd Trigger Level
...the world's most energy friendly microcontrollers BIAS Bias Current (µA) HALFBIAS=0 HALFBIAS=1 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111 23.3.3 Hysteresis In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When HYSTEN is set, the digital output will not toggle until the positive input voltage is at least 20mV above or below the negative input voltage.
Page 392 ...the world's most energy friendly microcontrollers 23.3.5 Interrupts and PRS Output The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in VCMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively.
Page 393: Register Map
...the world's most energy friendly microcontrollers 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 VCMP_CTRL Control Register 0x004 VCMP_INPUTSEL Input Selection Register 0x008 VCMP_STATUS Status Register 0x00C VCMP_IEN Interrupt Enable Register 0x010 VCMP_IF Interrupt Flag Register...
Page 394 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 512CYCLES 512 HFPERCLK cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HYSTEN Hysteresis Enable Enable hysteresis. Value Description No hysteresis...
Page 395 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VCMPOUT Voltage Supply Comparator Output Voltage supply comparator output value VCMPACT Voltage Supply Comparator Active Voltage supply comparator active status.
Page 396 ...the world's most energy friendly microcontrollers 23.5.6 VCMP_IFS - Interrupt Flag Set Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Set Write to 1 to set warm-up finished interrupt flag...
Page 397: Adc - Analog To Digital Converter
...the world's most energy friendly microcontrollers 24 ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features 8 external input channels 0 1 2 3 Why? In many applications there is a need to measure analog signals and record them in a digital representation, without exhausting your energy source.
Page 398: Functional Description
...the world's most energy friendly microcontrollers • Programmable scan sequence • Up to 8 configurable samples in scan sequence • Mask to select which pins are included in the sequence • Triggered by software or PRS input • One shot or repetitive mode •...
Page 399: Adc Overview
...the world's most energy friendly microcontrollers Figure 24.1. ADC Overview ADCn_CTRL ADCn_SINGLEDATA ADCn_CMD ADCn_SCANDATA ADCn_SINGLECTRL ADCn_STATUS ADCn_SCANCTRL Oversam pling filter Sequencer HFPERCLK ADC_CLK ADCn Prescaler Result buffer ADCn_CH0 ADCn_CH1 Control ADCn_CH2 ADCn_CH3 ADCn_CH4 ADCn_CH5 ADCn_CH6 ADCn_CH7 Tem p DAC0/ OPA0 DAC1/ OPA1 1.25 V 2.5 V...
Page 400: Adc Conversion Timing
...the world's most energy friendly microcontrollers Figure 24.2. ADC Conversion Timing HFPERCLK ADCn Prescaled clock (4x ) SINGLEAT/ ADC action Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCANAT...
Page 401 ...the world's most energy friendly microcontrollers Figure 24.3. ADC Analog Power Consumption With Different WARMUPMODE Settings Bandgap reference warm - up ADC warm - up ADC conversion ADC enabled Conversion trigger Conversion trigger Power NORMAL 5 µs Tim e 1 µs 1 µs Power KEEPSCANREFWARM 5 µs...
Page 402: Adc Temperature Measurement
...the world's most energy friendly microcontrollers Figure 24.4. ADC RC Input Filter Configuration Input 24.3.4.2 Temperature Measurement The ADC includes an internal temperature sensor. This sensor is characterized during production and the temperature readout from the ADC at production temperature, ADC0_TEMP_0_READ_1V25, is given in the Device Information (DI) page.
Page 403 ...the world's most energy friendly microcontrollers bitfields scale the current of ADC bandgap reference, and the COMPBIAS bits provide an additional bias programming for the ADC comparator as illustrated in Figure 24.5 (p. 403) . The electrical characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are given.
Page 404: Adc Conversion Tailgating
...the world's most energy friendly microcontrollers single sample just before a scan trigger can delay the start of the scan sequence, thus causing jitter in sample rate. To solve this, conversion tailgating can be chosen by setting TAILGATE in ADCn_CTRL. When this bit is set, any triggered single samples will wait for the next scan sequence to finish before activating (see Figure 24.6 (p.
Page 405 ...the world's most energy friendly microcontrollers Table 24.2. ADC Differential Conversion Results Input/Reference Binary Hex value 011111111111 0.25 001111111111 1/2048 000000000001 000000000000 -1/2048 111111111111 -0.25 101111111111 -0.5 100000000000 24.3.7.6 Resolution The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conversion by selecting a lower resolution (N = 6 or 8 bits).
Page 406 ...the world's most energy friendly microcontrollers 24.3.7.8 Adjustment By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read as 0.
Page 407: Calibration Register Effect
...the world's most energy friendly microcontrollers The effects of changing the calibration register values are given in Table 24.5 (p. 407) . Step by step calibration procedures for offset and gain are given in Section 24.3.10.1 (p. 407) and Section 24.3.10.2 (p. 407) . Table 24.5.
Page 408: Register Map
...the world's most energy friendly microcontrollers 24.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x004 ADCn_CMD Command Register 0x008 ADCn_STATUS Status Register 0x00C ADCn_SINGLECTRL Single Sample Control Register 0x010 ADCn_SCANCTRL Scan Control Register...
Page 409 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description X1024 1024 samples for each conversion result X2048 2048 samples for each conversion result X4096 4096 samples for each conversion result 23:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 TIMEBASE 0x1F...
Page 410 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANSTOP Scan Sequence Stop Write a 1 to stop scan sequence. SCANSTART Scan Sequence Start Write a 1 to start scan sequence.
Page 411 ...the world's most energy friendly microcontrollers Name Reset Access Description Reference selected for scan mode is warmed up. SINGLEREFWARM Single Reference Warmed Up Reference selected for single mode is warmed up. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANACT Scan Conversion Active Scan sequence is active or has pending conversions.
Page 412 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 128CYCLES 128 ADC_CLK cycles acquisition time for single sample 256CYCLES 256 ADC_CLK cycles acquisition time for single sample Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 Single Sample Reference Selection Select reference to ADC single sample mode.
Page 413 ...the world's most energy friendly microcontrollers Name Reset Access Description Single Sample Result Adjustment Select single sample result adjustment. Value Mode Description RIGHT Results are right adjusted LEFT Results are left adjusted DIFF Single Sample Differential Mode Select single ended or differential input. Value Description Single ended input...
Page 414 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 1CYCLE 1 ADC_CLK cycle acquisition time for scan samples 2CYCLES 2 ADC_CLK cycles acquisition time for scan samples 4CYCLES 4 ADC_CLK cycles acquisition time for scan samples 8CYCLES 8 ADC_CLK cycles acquisition time for scan samples 16CYCLES...
Page 415 ...the world's most energy friendly microcontrollers Name Reset Access Description Scan Sequence Result Adjustment Select scan sequence result adjustment. Value Mode Description RIGHT Results are right adjusted LEFT Results are left adjusted DIFF Scan Sequence Differential Mode Select single ended or differential input. Value Description Single ended input...
Page 416 ...the world's most energy friendly microcontrollers 24.5.7 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Indicates scan result overflow when this bit is set.
Page 417 ...the world's most energy friendly microcontrollers 24.5.9 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Clear Write to 1 to clear scan result overflow interrupt flag.
Page 418 ...the world's most energy friendly microcontrollers 24.5.11 ADCn_SCANDATA - Scan Conversion Result Data Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 Scan Conversion Result Data The register holds the results from the last scan conversion. Reading this field clears the SCANDV bit in the ADCn_STATUS register. 24.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset...
Page 419 ...the world's most energy friendly microcontrollers 24.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Scan Conversion Result Data Peek The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or single DMA request.
Page 420 ...the world's most energy friendly microcontrollers Name Reset Access Description This register contains the offset calibration value used with single conversions. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as a signed 2's complement number.
Page 421: Dac - Digital To Analog Converter
...the world's most energy friendly microcontrollers 25 DAC - Digital to Analog Converter Quick Facts What? The DAC is designed for low energy consumption, but can also provide very good performance. It can convert digital values 0 1 2 3 to analog signals at up to 500 kilo samples/ second and with 12-bit accuracy.
Page 422: Functional Description
...the world's most energy friendly microcontrollers • Output to ADC • Sine generation mode • Optional high strength line driver 25.3 Functional Description An overview of the DAC module is shown in Figure 25.1 (p. 422) . Figure 25.1. DAC Overview DACn_OUT0 Ch 0 CH0DATA...
Page 423: Dac Clock Prescaling
...the world's most energy friendly microcontrollers a combined data register, DACn_COMBDATA, where the data values for both channels can be written simultaneously. Writing to this register will start all enabled channels. If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data write, but when a positive one HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL in DACn_CHxCTRL.
Page 424: Dac Single Ended Output Voltage
...the world's most energy friendly microcontrollers Figure 25.2. DAC Bias Programming Reference BIASPROG Current HALFBIAS Internal DAC output bandgap buffer reference The minimum value of the BIASPROG bit-field of the DACn_BIASPROG register (i.e. BIASPROG=0b0000) represents the minimum bias current. Similarly BIASPROG=0b1111 represents the maximum bias current.
Page 425: Dac Sine Mode
...the world's most energy friendly microcontrollers table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be produced.
Page 426 ...the world's most energy friendly microcontrollers The DAC channels can also drive an alternative output network, which is described in the Opamp chapter in Section 26.3.1.2 (p. 444) . To enable this network, OUTMODE must be configured to ADC in DACn_CTRL. The actual output network can be configred by configuring DACn_OPAxMUX registers. 25.3.9 Calibration The DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gain correction can be written.
Page 427: Register Map
...the world's most energy friendly microcontrollers 25.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DACn_CTRL Control Register 0x004 DACn_STATUS Status Register 0x008 DACn_CH0CTRL Channel 0 Control Register 0x00C DACn_CH1CTRL Channel 1 Control Register 0x010 DACn_IEN...
Page 428 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 64CYCLES All channels with enabled refresh are refreshed every 64 prescaled cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 PRESC Prescaler Setting...
Page 429 ...the world's most energy friendly microcontrollers 25.5.2 DACn_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1DV Channel 1 Data Valid This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
Page 430 ...the world's most energy friendly microcontrollers Name Reset Access Description REFREN Channel 0 Automatic Refresh Enable Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL. Value Description Channel 0 is not refreshed automatically Channel 0 is refreshed automatically Channel 0 Enable Enable/disable channel 0.
Page 431 ...the world's most energy friendly microcontrollers 25.5.5 DACn_IEN - Interrupt Enable Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1UF Channel 1 Conversion Data Underflow Interrupt Enable Enable/disable channel 1 data underflow interrupt.
Page 432 ...the world's most energy friendly microcontrollers 25.5.7 DACn_IFS - Interrupt Flag Set Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1UF Channel 1 Data Underflow Interrupt Flag Set Write to 1 to set channel 1 Data Underflow interrupt flag.
Page 433 ...the world's most energy friendly microcontrollers 25.5.9 DACn_CH0DATA - Channel 0 Data Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 DATA 0x000...
Page 434 ...the world's most energy friendly microcontrollers Name Reset Access Description 27:16 CH1DATA 0x000 Channel 1 Data Data written to this register will be written to DATA in DACn_CH1DATA. 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 CH0DATA 0x000...
Page 435 ...the world's most energy friendly microcontrollers Name Reset Access Description Set this bit to halve the bias current. 13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:8 OPA2BIASPROG Bias Programming Value for OPA2 These bits control the bias current level.
Page 436 ...the world's most energy friendly microcontrollers Name Reset Access Description LPF DISABLE VALUE Description PLPFDIS Disables the low pass filter between positive pad and positive input. NLPFDIS Disables the low pass filter between negative pad and negative input. 11:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 437 ...the world's most energy friendly microcontrollers 25.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 RESSEL OPA0 Resistor Ladder Select...
Page 438 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX OPA0 Resistor Ladder Input Mux These bits selects the source for the input mux to the resistor ladder Value Mode Description...
Page 439 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Resistor Value Inverting Mode Gain (-R2/R1) Non-inverting Mode Gain (1+(R2/ RES4 R2 = 3 x R1 RES5 R2 = 4 1/3 x R1 -4 1/3 5 1/3 RES6 R2 = 7 x R1 RES7 R2 = 15 x R1...
Page 440 ...the world's most energy friendly microcontrollers Name Reset Access Description POSSEL OPA1 non-inverting Input Mux These bits selects the source for the non-inverting input on OPA1 Value Mode Description DISABLE Input disabled DAC as input POSPAD POS PAD as input OPA0INP OPA0 as input OPATAP...
Page 441 ...the world's most energy friendly microcontrollers Name Reset Access Description Connects pad to the negative input mux PPEN OPA2 Positive Pad Input Enable Connects pad to the positive input mux Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 RESINMUX OPA2 Resistor Ladder Input Mux...
Page 442: Opamp - Operational Amplifier
...the world's most energy friendly microcontrollers 26 OPAMP - Operational Amplifier Quick Facts What? The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With flexible gain and interconnection built- in programming they can be configured to support multiple common opamp functions, with all pins available externally for filter...
Page 443: Functional Description
...the world's most energy friendly microcontrollers • Cascaded Non-inverting PGA • Two Opamp Differential Amplifier • Three Opamp Differential Amplifier • Dual Buffer ADC Driver • Programmable gain 26.3 Functional Description The three opamps can be configured to perform various opamp functions through a network of muxes. An overview of the opamps are shown in Figure 26.1 (p.
Page 444: Opamp Overview
...the world's most energy friendly microcontrollers Figure 26.2. OPAMP Overview POSSEL[2:0] POS0 PPEN POSPAD NEXTOUT0 Main output OPA0TAP OPA0 Alternative output network NEXTOUT0 NEG0 NPEN NEGPAD NEGSEL[1:0] Unity gain OPA0TAP POSSEL[2:0] POS2 PPEN POSPAD NEXTOUT1 OPA0TAP NEXTOUT0 OPA2 Main output NEG2 NPEN RESINMUX[3:0]...
Page 445 ...the world's most energy friendly microcontrollers Figure 26.3. Opamp Output Stage Overview OPA0 Main output OPA1 Main output OPA2 Main outputs ADC CH5 input m ux OPA0 OPA1 OPA2 MAIN/ ALL MAIN/ ALL MAIN OUT0 output output output OPA0 OPA1 OPA2 OUT1 OPA0 Alternative...
Page 446: Voltage Follower Unity Gain Overview
...the world's most energy friendly microcontrollers MHz when driven from a 50 ohm source. The filter adds a parasitic capacitance of approximately 1.2 pF towards local VSS when enabled. The filter is enabled out of reset and can be disabled by setting OPAxLPFDIS in DACn_OPAxCTRL.
Page 447: Inverting Input Pga Overview
...the world's most energy friendly microcontrollers 26.3.2.3 Inverting input PGA Figure 26.5 (p. 447) shows the inverting input PGA configuration. In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to OPATAP in the DACn_OPAxMUX register.
Page 448: Cascaded Inverting Pga Overview
...the world's most energy friendly microcontrollers 26.3.2.5 Cascaded Inverting PGA This mode enables the opamp signals to be internally configured to cascade two or three opamps in inverting mode as shown in Figure 26.7 (p. 448) . In both cases the positive input will be configured to signal ground by setting OPAxPOSSEL bit-field to PAD in DACn_OPAx_MUX.
Page 449: Cascaded Non-Inverting Pga Configuration
...the world's most energy friendly microcontrollers the last stage can be created by setting NEXTOUT in DACn_OPA1MUX and OPA2POSSEL bit-field to OPA1INP in DACn_OPA2MUX. Figure 26.8. Cascaded Non-inverting PGA Overview VOUT1= VIN(1+ R2/ R1) VOUT2= VIN(1+ R2/ R1) VOUT3= VIN(1+ R2/ R1) Table 26.6.
Page 450: Opa0/Opa1 Differential Amplifier Configuration
...the world's most energy friendly microcontrollers Figure 26.9. Two Op-amp Differential Amplifier Overview OPA1 VDIFF= (V2- V1)R2/ R1 OPA0 OPA2 VDIFF= (V2- V1)R2/ R1 OPA1 Table 26.7. OPA0/OPA1 Differential Amplifier Configuration OPA bit-fields OPA Configuration OPA0 POSSEL POSPAD1 OPA0 NEGSEL OPA0 RESINMUX DISABLE...
Page 451: Three Opamp Differential Amplifier Gain Programming
...the world's most energy friendly microcontrollers OPA2 by setting the NEXTOUT bit-field in DACn_OPA1MUX and OPA2RESINMUX to OPA1INP in DACn_OPA2MUX. In addition the OPA2POSSEL must be set to 0PATAP. The OPA2 output can be configured by configuring the OUTPEN and OUTMODE bit-field. Figure 26.10.
Page 452: Register Description
...the world's most energy friendly microcontrollers setting OPATAP in DACn_OPAxMUX. The output from the opamps can be configured to connect to the ADC by setting OUTMODE to ALT or ALL in DACn_OPAxMUX. Figure 26.11. Dual Buffer ADC Driver Overview VOUTP= VIP(1+ R2/ R1) VOUTN= VIN(1+ R2/ R1) VOUTP = VIP (Unity Gain) VOUTN = VIN (Unity Gain)
Page 453: Aes - Advanced Encryption Standard Accelerator
How? I am fine !T4/ #2 High AES throughput allows the EFM32TG to spend more time in lower energy modes. In addition, specialized data access functions allow autonomous DMA/AES operation in both EM0 and EM1.
Page 454 ...the world's most energy friendly microcontrollers Figure 27.1. AES Key and Data Definitions Encryption PlainTex t CipherTex t Decryption Encryption PlainKey CipherKey Decryption 27.3.1 Encryption/Decryption The AES module can be set to encrypt or decrypt by clearing/setting the DECRYPT bit in AES_CTRL. The AES256 bit in AES_CTRL configures the size of the key used for encryption/decryption.
Page 455 ...the world's most energy friendly microcontrollers accessed through AES_KEYLn (n=A, B, C or D), while KEY7-KEY4 are accessed through KEYHn (n=A, B, C or D). Writing DATA3-DATA0 is then done through 4 consecutive writes to AES_DATA (or AES_XORDATA), starting with the word which is to be written to DATA0. For each write, the words will be word wise barrel shifted towards the least significant word.
Page 456 ...the world's most energy friendly microcontrollers • DATAWR: Cleared on a AES_DATA write or AES_CTRL write • XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write • DATARD: Cleared on a AES_DATA read or AES_CTRL write • KEYWR: Cleared on a AES_KEYHn write or AES_CTRL write 27.3.5 Block Chaining Example Example 27.1 (p.
Page 457: Register Map
...the world's most energy friendly microcontrollers 27.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AES_CTRL Control Register 0x004 AES_CMD Command Register 0x008 AES_STATUS Status Register 0x00C AES_IEN Interrupt Enable Register 0x010 AES_IF Interrupt Flag Register...
Page 458 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable/disable key buffer in AES-128 mode. AES256 AES-256 Mode Select AES-128 or AES-256 mode. Value Description AES-128 mode AES-256 mode DECRYPT Decryption/Encryption Mode Select encryption or decryption. Value Description AES Encryption AES Decryption 27.5.2 AES_CMD - Command Register Offset...
Page 459 ...the world's most energy friendly microcontrollers 27.5.4 AES_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Enable Enable/disable interrupt on encryption/decryption done.
Page 460 ...the world's most energy friendly microcontrollers 27.5.7 AES_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Flag Clear Write to 1 to clear encryption/decryption done interrupt flag...
Page 461 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 XORDATA 0x00000000 XOR Data Access Access data with XOR function through this register. 27.5.10 AES_KEYLA - KEY Low Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 KEYLA...
Page 462 ...the world's most energy friendly microcontrollers 27.5.12 AES_KEYLC - KEY Low Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:0 KEYLC 0x00000000 Key Low Access C Access the low key words through this register. 27.5.13 AES_KEYLD - KEY Low Register Offset Bit Position 0x03C...
Page 463 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 KEYHA 0x00000000 Key High Access A Access the high key words through this register. 27.5.15 AES_KEYHB - KEY High Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:0...
Page 464 ...the world's most energy friendly microcontrollers 27.5.17 AES_KEYHD - KEY High Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:0 KEYHD 0x00000000 Key High Access D Access the high key words through this register. www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 465: Gpio - General Purpose Input/Output
28.1 Introduction In the EFM32TG devices the General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins.
Page 466: Functional Description
...the world's most energy friendly microcontrollers • EM4 IO pin retention. This includes • Output enable • Output value • Pull enable • Pull direction • EM4 wake-up on selected GPIO pins • Glitch suppression input filter. • Analog connection to e.g. ADC or LCD. •...
Page 467: Pin Configuration
...the world's most energy friendly microcontrollers Figure 28.1. Pin Configuration Alternate function override Alternate function output enable Alternate function data out Port Control Output enable Output enable Data out Output value DOUT protection Pull- up enable Pull- down enable MODEn[3:0] Input enable ESD diode Filter enable...
Page 468 ...the world's most energy friendly microcontrollers MODEn Input Output DOUT Pull- Pull- Alt. Input Description down strength Filter Input enabled with pull-up 0b0011 Input enabled with pull-down and filter Input enabled with pull-up and filter 0b0100 Push-pull Push-pull 0b0101 Push-pull with alt. drive strength 0b0110 Open Open-source...
Page 469 ...the world's most energy friendly microcontrollers Figure 28.3. Push-Pull Configuration Output Enable DOUT Input Enable When MODEn is 0110 or 0111, the pin operates in open-source mode, the latter with a pull-down resistor. When driving a high value in open-source mode, the pull-down is disconnected to save power. For the remaining MODEn values, i.e.
Page 470: Em4 Wu Register Bits To Pin Mapping
...the world's most energy friendly microcontrollers pin, the input filter is enabled during EM4. This is done to avoid false wake-up caused by glitches. In addition, the polarity of the EM4 wake-up request can be selected using the GPIO_EM4WUPOL register. Figure 28.5.
Page 471 ...the world's most energy friendly microcontrollers function’s output data and output enable signals override the data output and output enable signals from the GPIO. However, the pin configuration stays as set in GPIO_Px_MODEL, GPIO_Px_MODEH and GPIO_Px_DOUT registers. I.e. the pin configuration must be set to output enable in GPIO for a peripheral to be able to use the pin as an output.
Page 472 ...the world's most energy friendly microcontrollers while the odd is triggered by odd flags. The interrupt flags can be set and cleared by software by writing the GPIO_IFS and GPIO_IFC registers, see Example 28.1 (p. 472) . Since the external interrupts are asynchronous, they are sensitive to noise.
Page 473: Register Map
...the world's most energy friendly microcontrollers 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL Port Control Register 0x004 GPIO_PA_MODEL Port Pin Mode Low Register 0x008 GPIO_PA_MODEH Port Pin Mode High Register 0x00C GPIO_PA_DOUT Port Data Out Register...
Page 474: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 GPIO_PE_DOUTSET Port Data Out Set Register 0x0A4 GPIO_PE_DOUTCLR Port Data Out Clear Register 0x0A8 GPIO_PE_DOUTTGL Port Data Out Toggle Register 0x0AC GPIO_PE_DIN Port Data In Register 0x0B0 GPIO_PE_PINLOCKN Port Unlocked Pins Register 0x0B4 GPIO_PF_CTRL Port Control Register...
Page 475 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DRIVEMODE Drive Mode Select Select drive mode for all pins on port configured with alternate drive strength. Value Mode Description...
Page 476 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description WIREDANDDRIVEFILTER Open-drain output with filter and drive-strength set by DRIVEMODE WIREDANDDRIVEPULLUP Open-drain output with pullup and drive-strength set by DRIVEMODE WIREDANDDRIVEPULLUPFILTER Open-drain output with filter, pullup and drive-strength set by DRIVEMODE 28.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Offset Bit Position...
Page 477 ...the world's most energy friendly microcontrollers 28.5.4 GPIO_Px_DOUT - Port Data Out Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUT 0x0000...
Page 478 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTCLR 0x0000 Data Out Clear Write bits to 1 to clear corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 28.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register Offset Bit Position...
Page 479 ...the world's most energy friendly microcontrollers 28.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 PINLOCKN 0xFFFF...
Page 480 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:20 EXTIPSEL5 External Interrupt 5 Port Select Select input port for external interrupt 5. Value Mode Description...
Page 481 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTF Port F pin 1 selected for external interrupt 1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EXTIPSEL0 External Interrupt 0 Port Select Select input port for external interrupt 0.
Page 482 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTA Port A pin 13 selected for external interrupt 13 PORTB Port B pin 13 selected for external interrupt 13 PORTC Port C pin 13 selected for external interrupt 13 PORTD Port D pin 13 selected for external interrupt 13 PORTE...
Page 483 ...the world's most energy friendly microcontrollers Name Reset Access Description Select input port for external interrupt 8. Value Mode Description PORTA Port A pin 8 selected for external interrupt 8 PORTB Port B pin 8 selected for external interrupt 8 PORTC Port C pin 8 selected for external interrupt 8 PORTD...
Page 484 ...the world's most energy friendly microcontrollers Name Reset Access Description Set bit n to enable triggering of external interrupt n on falling edge. Value Description EXTIFALL[n] = 0 Falling edge trigger disabled EXTIFALL[n] = 1 Falling edge trigger enabled 28.5.14 GPIO_IEN - Interrupt Enable Register Offset Bit Position 0x110...
Page 485 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description EXT[n] = 1 Pin n external interrupt flag set 28.5.16 GPIO_IFS - Interrupt Flag Set Register Offset Bit Position 0x118 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 486 ...the world's most energy friendly microcontrollers 28.5.18 GPIO_ROUTE - I/O Routing Register Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SWLOCATION I/O Location Decides the location of the SW pins.
Page 487 ...the world's most energy friendly microcontrollers 28.5.20 GPIO_LOCK - Configuration Lock Register Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000...
Page 488 ...the world's most energy friendly microcontrollers 28.5.22 GPIO_CMD - GPIO Command Register Offset Bit Position 0x130 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EM4WUCLR EM4 Wake-up clear Write 1 to clear all wake-up requests.
Page 489 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EM4WUPOL 0x00 EM4 Wake-up Polarity Write bit n to 1 for high wake-up request. Write bit n to 0 for low wake-up request Value Mode Description...
Page 490: Lcd - Liquid Crystal Display Driver
EM2 for long periods. Adding the flexible frame rate setting, contrast control, and different multiplexing modes make the EFM32TG the optimal choice for battery- driven systems with LCD panels. 29.1 Introduction The LCD driver is capable of driving a segmented LCD display combination of: 1x24, 2x24, 3x24, 4x24, 6x22 or 8x20 segments.
Page 491: Functional Description
...the world's most energy friendly microcontrollers • LCD frame interrupt • Direct segment control 29.3 Functional Description An overview of the LCD module is shown in Figure 29.1 (p. 491) . In its simplest form, an LCD driver would apply a voltage above a certain threshold voltage in order to darken a segment and a voltage below threshold to make a segment clear.
Page 492: Lcd Mux Settings
...the world's most energy friendly microcontrollers Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. 29.3.2 Multiplexing, Bias, and Wave Settings The LCD driver supports different multiplexing and bias settings, and these can be set individually in the MUX and BIAS bits in LCD_DISPCTRL respectively, see Table 29.1 (p.
Page 493: Lcd Wave Settings
...the world's most energy friendly microcontrollers Table 29.3. LCD Wave Settings WAVE Mode Wave mode LowPower Low power optimized waveform output Normal Regular waveform output Figure 29.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias (2/ 3V (1/ 3V Fram e Start Fram e End...
Page 494 ...the world's most energy friendly microcontrollers 29.3.3.2 Waveforms with 1/2 Bias and Duplex Multiplexing In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/2 bias and duplex multiplexing (waveforms show two frames) Figure 29.5.
Page 495 ...the world's most energy friendly microcontrollers 1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) • V = 0.79 × V LCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform. Figure 29.9.
Page 496 ...the world's most energy friendly microcontrollers Figure 29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels.
Page 497 ...the world's most energy friendly microcontrollers Figure 29.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) •...
Page 498 ...the world's most energy friendly microcontrollers Figure 29.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2 (1/ 2V Fram e Start Fram e End 1/2 bias and triplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels.
Page 499 ...the world's most energy friendly microcontrollers 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) • V = 0.7 V LCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform Figure 29.23.
Page 500 ...the world's most energy friendly microcontrollers Figure 29.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2 (2/ 3V (1/ 3V Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0...
Page 501 ...the world's most energy friendly microcontrollers Figure 29.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM1 • DC voltage = 0 (over one frame) •...
Page 502 ...the world's most energy friendly microcontrollers Figure 29.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.35.
Page 503 ...the world's most energy friendly microcontrollers Figure 29.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection com 0 com 1 com 2 com 3 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM0...
Page 504 ...the world's most energy friendly microcontrollers Figure 29.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) •...
Page 505: Lcd Contrast
...the world's most energy friendly microcontrollers adjusts the V . The contrast is set by CONLEV in LCD_DISPCTRL, and can be adjusted relative LCD_OUT to either V ) or Ground using CONCONF in LCD_DISPCTRL. See Table 29.4 (p. 505) and Table 29.5 (p.
Page 506: Lcd Principle Of Contrast Adjustment For Different Bias Settings
...the world's most energy friendly microcontrollers Table 29.6. LCD Principle of Contrast Adjustment for Different Bias Settings. Contrast adjustment Contrast adjustment No contrast adjustment relative to V relative to GND (CONLEV = 11111) (CONCONF = 0) (CONCONF = 1) 1/4 bias LCD_OUT LCD_OUT LCD_OUT...
Page 507: Lcd
...the world's most energy friendly microcontrollers 29.3.5 V Selection By default, the LCD driver runs on main external power (V ), see Table 29.7 (p. 507) . An internal boost circuit can be enabled by setting VBOOSTEN in CMU_LCDCTRL and selecting the boosted voltage by setting VLCDSEL in LCD_DISPCTRL.
Page 508: Lcd Frame Rate Conversion Table
...the world's most energy friendly microcontrollers • LFCLK16: LFACLK = LFACLK/16 LCDpre • LFCLK32: LFACLK = LFACLK/32 LCDpre • LFCLK64: LFACLK = LFACLK/64 LCDpre • LFCLK128: LFACLK = LFACLK/128 LCDpre In addition to selecting the correct prescaling, the clock source can be selected in the CMU. To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
Page 509: Lcd Update Data Control (Udctrl) Bits
...the world's most energy friendly microcontrollers Table 29.10. LCD Update Data Control (UDCTRL) Bits UDCTRL Mode Description REGULAR The data transfer is controlled by SW and data synchronization is initiated by writing data to the buffers. Data is transferred as soon as possible, possibly creating a frame with a DC component on the LCD.
Page 510: Fcpresc
...the world's most energy friendly microcontrollers Table 29.12. FCPRESC FCPRESC Mode Description General equation Div1 FRAME Div2 FRAME FCPRESC = CLK FRAME Div4 FRAME Div8 FRAME The top value for the Frame Counter is set by FCTOP in LCD_BACTRL. Every time the frame counter reaches zero, it is reloaded with the top value, and at the same time an event, which can cause an interrupt, data update, blink, or an animation state transition is triggered.
Page 511: Lcd Animation Shift Register
...the world's most energy friendly microcontrollers 29.3.12 Blink, Blank, and Animation Features 29.3.12.1 Blink The LCD driver can be configured to blink, alternating all enabled segments between on and off. The blink frequency is given by the CLK frequency, see Section 29.3.10 (p. 509) . See Section 29.3.8 (p. EVENT 508) for details regarding synchronization of the blink feature.
Page 512: Lcd Animation Example
...the world's most energy friendly microcontrollers Table 29.15. LCD Animation Example ASTATE LCD_AREGA LCD_AREGB Resulting Data 11000000 11000000 11000000 01100000 11000000 11100000 01100000 01100000 01100000 00110000 01100000 01110000 00110000 00110000 00110000 00011000 00110000 00111000 00011000 00011000 00011000 00001100 00011000 00011100 00001100 00001100 00001100...
Page 513 ...the world's most energy friendly microcontrollers Example 29.2. LCD Animation Enable Example • Write data into the animation registers LCD_AREGA, LCD_AREGB • Enable the correct shift direction (if any) • Decide which logical function to perform on the registers • ALOGSEL = 0: Data_out = LCD_AREGA & LCD_AREGB •...
Page 514: Register Map
...the world's most energy friendly microcontrollers 29.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LCD_CTRL Control Register 0x004 LCD_DISPCTRL Display Control Register 0x008 LCD_SEGEN Segment Enable Register 0x00C LCD_BACTRL Blink and Animation Control Register 0x010 LCD_STATUS...
Page 515 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description DSC enable 22:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) UDCTRL Update Data Control These bits control how data from the SEGDn registers are transferred to the LCD driver. Value Mode Description...
Page 516: Bias Configuration
...the world's most energy friendly microcontrollers Name Reset Access Description CONCONF Contrast Configuration This bit selects whether the contrast adjustment is done relative to V or Ground. Value Mode Description VLCD Contrast is adjusted relative to V Contrast is adjusted relative to Ground 14:13 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 517 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGEN 0x000 Segment Enable Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X to X+3, set bit X/4, i.e.
Page 518 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SHIFTLEFT Animation Register A is shifted left SHIFTRIGHT Animation Register A is shifted right Animation Enable When this bit is set, the animate function is enabled. BLANK Blank Display When this bit is set, all segment output waveforms are configured to blank the LCD display.
Page 519 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) AREGA 0x00 Animation Register A Data This register contains the A data for generating animation pattern. 29.5.7 LCD_AREGB - Animation Register B (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 520 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Frame Counter Interrupt Flag Set Write to 1 to set FC interrupt flag. 29.5.10 LCD_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 521 ...the world's most energy friendly microcontrollers Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD0L 0x000000 COM0 Segment Data Low This register contains segment data for segment lines 0-23 for COM0.
Page 522 ...the world's most energy friendly microcontrollers Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD2L 0x000000 COM2 Segment Data Low This register contains segment data for segment lines 0-23 for COM2.
Page 523 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the LCD is postponed until this bit is cleared. Use this bit to update several registers simultaneously. Value Mode Description...
Page 524 ...the world's most energy friendly microcontrollers 29.5.18 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x0CC Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 525 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0D4 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 SEGD6L 0x000000 COM6 Segment Data This register contains segment data for segment lines 0-23 for COM6.
Page 526: Revision History
...the world's most energy friendly microcontrollers 30 Revision History 30.1 Revision 1.20 July 2nd, 2014 Added QFP part numbers to Product Overview table. Updated current numbers and voltage supply range. Moved chapter "Device Revision" to section 3. 30.2 Revision 1.10 August 22nd, 2013 Corrected UART data frame rate.
Page 527: Revision 1.00
Updated description of the Low Pass Filter on the input of the Opamps. Corrected COM4-COM7 SEG line placement. Corrected I2S Mono waveform. Corrected the I2C Clock Modes FAST value to 14:9. Corrected EFM32TG Microcontroller Series table. Updated HFXO/LFXO description. www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 528: Revision 0.90
...the world's most energy friendly microcontrollers Updated EM0-EM4 current consumption. 30.4 Revision 0.90 December 21th, 2010 Major updates to all chapters. 30.5 Revision 0.80 October 1st, 2010 Initial preliminary revision. www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 529: Abbreviations
...the world's most energy friendly microcontrollers A Abbreviations A.1 Abbreviations This section lists abbreviations used in this document. Table A.1. Abbreviations Abbreviation Description ACMP Analog Comparator Analog to Digital Converter AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architecture".
Page 530 ...the world's most energy friendly microcontrollers Abbreviation Description LFRCO Low Frequency RC Oscillator LFXO Low Frequency Crystal Oscillator Low-speed Media Access Controller NVIC Nested Vector Interrupt Controller OPA/OPAMP Operational Amplifier Oversampling Ratio On-the-go PCNT Pulse Counter Programmable Gain Array Physical Layer Peripheral Reflex System PSRR Power Supply Rejection Ratio...
Page 531: Disclaimer And Trademarks
A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Page 532: Contact Information
...the world's most energy friendly microcontrollers C Contact Information Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: http://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. www.silabs.com 2014-07-02 - Tiny Gecko Family - d0034_Rev1.20...
Page 533: Table Of Contents
...the world's most energy friendly microcontrollers Table of Contents 1. Energy Friendly Microcontrollers ........................2 1.1. Typical Applications ......................... 2 1.2. EFM32TG Development ........................2 2. About This Document ..........................3 2.1. Conventions ........................... 3 2.2. Related Documentation ........................4 3.
Page 534 ...the world's most energy friendly microcontrollers 13.2. Features ..........................135 13.3. Functional Description ........................ 135 13.4. Register Map ..........................140 13.5. Register Description ........................140 14. I C - Inter-Integrated Circuit Interface ....................... 145 14.1. Introduction ..........................145 14.2. Features ..........................145 14.3.
Page 535 ...the world's most energy friendly microcontrollers 25.4. Register Map ..........................427 25.5. Register Description ........................427 26. OPAMP - Operational Amplifier ....................... 442 26.1. Introduction ..........................442 26.2. Features ..........................442 26.3. Functional Description ........................ 443 26.4. Register Description ........................452 26.5.
Page 536 ...the world's most energy friendly microcontrollers List of Figures 3.1. Block Diagram of EFM32TG ........................7 3.2. Energy Mode Indicator ..........................7 3.3. Revision Number Extraction ........................10 4.1. Interrupt Operation ..........................12 5.1. EFM32TG Bus System .......................... 15 5.2. System Address Space .......................... 16 5.3.
Page 537 ...the world's most energy friendly microcontrollers 16.5. LEUART Local Loopback ........................234 16.6. LEUART Half Duplex Communication with External Driver ................. 234 16.7. LEUART - NRZ vs. RZI ........................236 17.1. TIMER Block Overview ........................252 17.2. TIMER Hardware Timer/Counter Control ....................254 17.3.
Page 538 ...the world's most energy friendly microcontrollers 26.8. Cascaded Non-inverting PGA Overview ....................449 26.9. Two Op-amp Differential Amplifier Overview ................... 450 26.10. Three Op-amp Differential Amplifier Overview ..................451 26.11. Dual Buffer ADC Driver Overview ....................... 452 27.1. AES Key and Data Definitions ......................454 27.2.
Page 539 List of Tables 2.1. Register Access Types ..........................3 3.1. Energy Mode Description ......................... 8 3.2. EFM32TG Microcontroller Series ....................... 8 3.3. Minor Revision Number Interpretation ....................... 10 4.1. Interrupt Request Lines (IRQ) ........................12 5.1. Memory System Core Peripherals ......................17 5.2.
Page 540 ...the world's most energy friendly microcontrollers 26.3. Inverting input PGA Configuration ......................447 26.4. Non-inverting PGA Configuration ......................447 26.5. Cascaded Inverting PGA Configuration ....................448 26.6. Cascaded Non-inverting PGA Configuration .................... 449 26.7. OPA0/OPA1 Differential Amplifier Configuration ..................450 26.8.
Page 541 ...the world's most energy friendly microcontrollers List of Examples 8.1. DMA Transfer ............................66 15.1. USART Multi-processor Mode Example ....................193 19.1. LETIMER Triggered Output Generation ....................304 19.2. LETIMER Continuous Output Generation ....................305 19.3. LETIMER PWM Output ........................306 19.4.
Page 542 ...the world's most energy friendly microcontrollers List of Equations 5.1. Memory SRAM Area Set/Clear Bit ......................16 5.2. Memory Peripheral Area Bit Modification ....................17 5.3. Memory Wait Cycles with Clock Equal or Faster than HFCORECLK ............... 20 5.4. Memory Wait Cycles with Clock Slower than CPU ..................20 12.1.