Spi0Pcf: Spi0 Pin Configuration - Silicon Laboratories EFM8 Series Reference Manual

17.4.8 SPI0PCF: SPI0 Pin Configuration

Bit 7
Name SCKSEL
Access RW
Reset 0x0
SFR Page = 0x20; SFR Address: 0xDF
Bit Name
7:6 SCKSEL
This field selects the source of the SCK input signal in slave mode.
Value
0x0
0x1
0x2
0x3
5 Reserved
4:3 MISEL
Value
0x0
0x1
0x2
0x3
2 Reserved
1:0 SISEL
This field selects the source of the MOSI clock signal in slave mode.
Value
0x0
0x1
0x2
0x3
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6 5
Reserved
R
0
Reset Access Description
0x0 RW Slave Clock Input Select.
Name Description
CROSSBAR The crossbar input is the SCK input (slave mode).
CLU1 The CLU1 synchronous output is the SCK input (slave mode).
CLU2 The CLU2 synchronous output is the SCK input (slave mode).
CLU3 The CLU3 synchronous output is the SCK input (slave mode).
Must write reset value.
0x0 RW Master MISO Input Select.
Name Description
CROSSBAR The crossbar input is the MISO input (master mode).
CLU0 The CLU0 synchronous output is the MISO input (master mode).
CLU2 The CLU2 synchronous output is the MISO input (master mode).
CLU3 The CLU3 synchronous output is the MISO input (master mode).
Must write reset value.
0x0 RW Slave MOSI Input Select.
Name Description
CROSSBAR The crossbar input is the MOSI input (slave mode).
CLU0 The CLU0 synchronous output is the MOSI input (slave mode).
CLU1 The CLU1 synchronous output is the MOSI input (slave mode).
CLU3 The CLU3 synchronous output is the MOSI input (slave mode).
4 3
MISEL Reserved
RW
0x0
EFM8UB3 Reference Manual
Serial Peripheral Interface (SPI0)
2 1
SISEL
R RW
0 0x0
Rev. 0.2 | 231
0