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EFM32 Jade Gecko Family
EFM32JG1 Reference Manual
The EFM32 Jade Gecko MCUs are the world's most energy-
friendly microcontrollers.
EFM32JG1 features a powerful 32-bit ARM
erals, including a unique cryptographic hardware engine supporting AES, ECC, and
SHA. These features, combined with ultra-low current active mode and short wake-up
time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any
battery-powered application, as well as other systems requiring high performance and
low-energy consumption.
Example applications:
• IoT devices and sensors
• Health and fitness
• Smart accessories
Core / Memory
ARM Cortex
TM
M3 processor
Flash Program
RAM Memory
Memory
Serial Interfaces
External Interrupts
USART
General Purpose I/O
Low Energy UART
TM
I
2
C
Lowest power mode with peripheral operational:
EM1 - Sleep
EM0 - Active
silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
®
Cortex-M3 and a wide selection of periph-
• Home automation and security
• Industrial and factory automation
Memory
Protection Unit
Debug Interface
DMA Controller
Peripheral Reflex System
I/O Ports
Timers and Triggers
Timer/Counter
Pulse Counter
Pin Reset
Watchdog Timer
Pin Wakeup
EM2 – Deep Sleep
Clock Management
High Frequency
High Frequency
Crystal
RC Oscillator
Oscillator
Auxiliary High
Low Frequency
Frequency RC
RC Oscillator
Oscillator
Low Frequency
Ultra Low
Crystal
Frequency RC
Oscillator
Oscillator
32-bit bus
Analog Interfaces
Low Energy Timer
Real Time Counter
and Calendar
CRYOTIMER
EM3 - Stop
ENERGY FRIENDLY FEATURES
• ARM Cortex-M3 at 40 MHz
• Ultra low energy operation:
• 2.1 μA EM3 Stop current (CRYOTIMER
running with state/RAM retention)
• 2.5 μA EM2 DeepSleep current (RTCC
running with state and RAM retention)
• 63 μA/MHz in Energy Mode 0 (EM0)
• Hardware cryptographic engine supports
AES, ECC, and SHA
• Integrated dc-dc converter
• CRYOTIMER operates down to EM4
• 5 V tolerant I/O
Energy Management
Voltage
Voltage Monitor
Regulator
DC-DC
Power-On Reset
Converter
Brown-Out
Detector
Other
ADC
CRYPTO
Analog Comparator
CRC
IDAC
EM4 - Shutoff
EM4 - Hibernate
Preliminary Rev. 0.6
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Summary of Contents for Silicon Laboratories EFM32JG1
- Page 1 SHA. These features, combined with ultra-low current active mode and short wake-up running with state/RAM retention) time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any • 2.5 μA EM2 DeepSleep current (RTCC battery-powered application, as well as other systems requiring high performance and running with state and RAM retention) low-energy consumption.
-
Page 2: About This Document
EFM32JG1 Reference Manual About This Document 1. About This Document 1.1 Introduction This document contains reference material for the EFM32 Jade Gecko devices. All modules and peripherals in the EFM32 Jade Gecko devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such differences, including pinout, are covered in the device data sheets. -
Page 3: Conventions
EFM32JG1 Reference Manual About This Document 1.2 Conventions Register Names Register names are given with a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the module number for modules which can exist in more than one instance. -
Page 4: Related Documentation
EFM32JG1 Reference Manual About This Document Reset Value The reset value denotes the value after reset. Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations on these registers before they are initialized results in undefined register values. -
Page 5: System Overview
EFM32JG1 Reference Manual System Overview 2. System Overview Quick Facts What? 0 1 2 3 The EFM32 Jade Gecko is a highly integrated, con- figurable and low power MCU with a complete set of peripherals. Why? EFM32 Jade Gecko features an Cortex-M3 core, a... -
Page 6: Block Diagrams
EFM32JG1 Reference Manual System Overview 2.2 Block Diagrams The block diagram for the EFM32 Jade Gecko MCU series is shown in (Figure 2.1 EFM32 Jade Gecko System-On-Chip Block Diagram on page Core / Memory Clock Management Energy Management High Frequency... -
Page 7: Mcu Features Overview
EFM32JG1 Reference Manual System Overview 2.3 MCU Features overview • ARM Cortex-M3 CPU platform • High Performance 32-bit processor @ up to 40 MHz • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System • Power routing configurations including DCDC control •... -
Page 8: Oscillators And Clocks
EFM32JG1 Reference Manual System Overview • Single ended or differential operation • Conversion tailgating for predictable latency • Current Digital to Analog Converter • Source or sink a configurable constant current • 2× Analog Comparator • Programmable speed/current • Capacitive sensing with up to 8 inputs •... -
Page 9: Data Encryption And Authentication
EFM32JG1 Reference Manual System Overview 2.6 Data Encryption and Authentication EFM32 Jade Gecko has hardware support for AES encryption, decryption and authentication modes. These security operations can be performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits. -
Page 10: Timers
EFM32JG1 Reference Manual System Overview 2.7 Timers EFM32 Jade Gecko includes multiple timers, as can be seen from Table 2.3 EFM32 Jade Gecko Timers Overview on page Table 2.3. EFM32 Jade Gecko Timers Overview Timer Number of instances Typical clock source... -
Page 11: System Processor
EFM32JG1 Reference Manual System Processor 3. System Processor Quick Facts What? 0 1 2 3 The industry leading Cortex-M3 processor from ARM is the CPU in the EFM32 Jade Gecko devices. Why? The ARM Cortex-M3 is designed for exceptionally short response time, high code density, and high 32-... -
Page 12: Features
EFM32JG1 Reference Manual System Processor 3.2 Features • Harvard architecture • Separate data and program memory buses (No memory bottleneck as in a single bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density •... -
Page 13: Interrupt Operation
EFM32JG1 Reference Manual System Processor 3.3.1 Interrupt Operation Module Cortex-M4 NVIC IFS[n] IFC[n] IEN[n] SETENA[n]/CLRENA[n] Active interrupt Interrupt clear Interrupt request IF[n] condition clear SETPEND[n]/CLRPEND[n] Software generated interrupt Figure 3.1. Interrupt Operation The interrupt request (IRQ) lines are connected to the Cortex-M3. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ) -
Page 14: Interrupt Request Lines (Irq)
EFM32JG1 Reference Manual System Processor 3.3.2 Interrupt Request Lines (IRQ) Table 3.1. Interrupt Request Lines (IRQ) IRQ # Source WDOG0 LDMA GPIO_EVEN TIMER0 USART0_RX USART0_TX ACMP0 ADC0 IDAC0 I2C0 GPIO_ODD TIMER1 USART1_RX USART1_TX LEUART0 PCNT0 CRYPTO LETIMER0 RTCC CRYOTIMER FPUEH silabs.com | Smart. -
Page 15: Memory And Bus System
EFM32JG1 Reference Manual Memory and Bus System 4. Memory and Bus System Quick Facts What? 0 1 2 3 A low latency memory system including low energy Flash and RAM with data retention which makes the energy modes attractive. Why? -
Page 16: Functional Description
EFM32JG1 Reference Manual Memory and Bus System 4.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Fig- ure 4.2 System Address Space with Core and Code Space Listing on page Figure 4.2. - Page 17 EFM32JG1 Reference Manual Memory and Bus System Figure 4.3. System Address Space with Peripheral Listing The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32 Jade Gecko. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus interface to fetch instructions. This results in reduced performance as the Cortex-M3 accesses stack, other data in SRAM and peripherals using the System bus interface.
-
Page 18: Bit-Banding
EFM32JG1 Reference Manual Memory and Bus System 4.2.1 Bit-banding The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and write operations to these regions are converted into masked single-bit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EFM32 Jade Gecko. -
Page 19: Peripheral Bit Set And Clear
EFM32JG1 Reference Manual Memory and Bus System 4.2.2 Peripheral Bit Set and Clear The EFM32 Jade Gecko supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that Do Not Support Bit Set and Bit Clear on page 18. -
Page 20: Peripherals
EFM32JG1 Reference Manual Memory and Bus System 4.2.3 Peripherals The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Periph- erals on page Table 4.3 Low Energy Peripherals on page 19 , and Table 4.4 Core Peripherals on page... -
Page 21: Arbitration
EFM32JG1 Reference Manual Memory and Bus System 4.2.4.1 Arbitration The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency, while starvation of simultane- ous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states during peak interaction. -
Page 22: Bus Faults
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. There are two different synchronization mechanisms on the EFM32JG1, immedi- ate synchronization, and delayed synchronization. Immediate synchronization is available for the RTCC and LETIMER, and results in an immediate update of the target registers. -
Page 23: Delayed Synchronization
EFM32JG1 Reference Manual Memory and Bus System 4.3.1.1 Delayed Synchronization After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corre- sponding busy flag in the <module_name>_SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as syn- chronization is in progress and is cleared upon completion. -
Page 24: Reading
EFM32JG1 Reference Manual Memory and Bus System 4.3.2 Reading When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates in the Low Energy clock domain or High Frequency clock domain. See Figure 4.10 Read operation from Low Energy Peripherals on page 23 for an overview of the reading operation. -
Page 25: Sram
EFM32JG1 Reference Manual Memory and Bus System 4.5 SRAM The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may be set up to transfer data between the SRAM, Flash and peripherals. -
Page 26: Di Page Entry Map
EFM32JG1 Reference Manual Memory and Bus System 4.6 DI Page Entry Map The DI page contains production calibration data as well as device identification information. See the peripheral chapters for how each calibration value is to be used with the associated peripheral. -
Page 27: Di Page Entry Description
EFM32JG1 Reference Manual Memory and Bus System Offset Name Type Description 0x158 IDAC0CAL0 IDAC0 Calibration Register 0 0x15C IDAC0CAL1 IDAC0 Calibration Register 1 0x168 DCDCLNVCTRL0 DCDC Low-noise VREF Trim Register 0 0x16C DCDCLPVCTRL0 DCDC Low-power VREF Trim Register 0 0x170... -
Page 28: Eui48L - Eui48 Oui And Unique Identifier
EFM32JG1 Reference Manual Memory and Bus System 4.7.2 EUI48L - EUI48 OUI and Unique identifier Offset Bit Position 0x028 Access Name Name Access Description 31:24 OUI48L Lower Octet of EUI48 Organizationally Unique Identi- fier 23:0 UNIQUEID Unique identifier 4.7.3 EUI48H - OUI... -
Page 29: Meminfo - Flash Page Size And Misc. Chip Information
EFM32JG1 Reference Manual Memory and Bus System 4.7.5 MEMINFO - Flash page size and misc. chip information Offset Bit Position 0x034 Access Name Name Access Description 31:24 FLASH_PAGE_SIZE Flash page size in bytes coded as 2 ^ ((MEM_IN- FO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes. -
Page 30: Uniquel - Low 32 Bits Of Device Unique Number
EFM32JG1 Reference Manual Memory and Bus System 4.7.6 UNIQUEL - Low 32 bits of device unique number Offset Bit Position 0x040 Access Name Name Access Description 31:0 UNIQUEL Low 32 bits of device unique number 4.7.7 UNIQUEH - High 32 bits of device unique number... -
Page 31: Part - Part Description
EFM32JG1 Reference Manual Memory and Bus System 4.7.9 PART - Part description Offset Bit Position 0x04C Access Name Name Access Description 31:24 PROD_REV Production revision as unsigned integer 23:16 DEVICE_FAMILY Device Family Value Mode Description EFR32MG1P EFR32 Mighty Gecko Gen1 Device Family... -
Page 32: Devinforev - Device Information
EFM32JG1 Reference Manual Memory and Bus System Name Access Description EFM32PG1B EFM32 Pearl Gecko Gen1 Device Family EFM32JG1B EFM32 Jade Gecko Gen1 Device Family EZR32LG EZR32 Leopard Gecko Device Family EZR32WG EZR32 Wonder Gecko Device Family EZR32HG EZR32 Happy Gecko Device Family... -
Page 33: Adc0Cal0 - Adc0 Calibration Register 0
EFM32JG1 Reference Manual Memory and Bus System 4.7.12 ADC0CAL0 - ADC0 calibration register 0 Offset Bit Position 0x060 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN2V5 Gain for 2.5V reference 23:20 NEGSEOFFSET2V5 Negative single ended offset for 2.5V reference... -
Page 34: Adc0Cal1 - Adc0 Calibration Register 1
EFM32JG1 Reference Manual Memory and Bus System 4.7.13 ADC0CAL1 - ADC0 calibration register 1 Offset Bit Position 0x064 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN5VDIFF Gain for for 5V differential reference 23:20 NEGSEOFFSET5VDIFF Negative single ended offset with for 5V differential... -
Page 35: Adc0Cal2 - Adc0 Calibration Register 2
EFM32JG1 Reference Manual Memory and Bus System 4.7.14 ADC0CAL2 - ADC0 calibration register 2 Offset Bit Position 0x068 Access Name Name Access Description Reserved Reserved for future use 30:24 Reserved Reserved for future use 23:20 Reserved Reserved for future use... -
Page 36: Hfrcocal0 - Hfrco Calibration Register (4 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.16 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) Offset Bit Position 0x080 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 37: Hfrcocal3 - Hfrco Calibration Register (7 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.17 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) Offset Bit Position 0x08C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 38: Hfrcocal6 - Hfrco Calibration Register (13 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.18 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) Offset Bit Position 0x098 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 39: Hfrcocal7 - Hfrco Calibration Register (16 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.19 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) Offset Bit Position 0x09C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 40: Hfrcocal8 - Hfrco Calibration Register (19 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.20 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) Offset Bit Position 0x0A0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 41: Hfrcocal10 - Hfrco Calibration Register (26 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.21 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) Offset Bit Position 0x0A8 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 42: Hfrcocal11 - Hfrco Calibration Register (32 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.22 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) Offset Bit Position 0x0AC Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 43: Hfrcocal12 - Hfrco Calibration Register (38 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.23 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) Offset Bit Position 0x0B0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning... -
Page 44: Auxhfrcocal0 - Auxhfrco Calibration Register (4 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.24 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) Offset Bit Position 0x0E0 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 45: Auxhfrcocal3 - Auxhfrco Calibration Register (7 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.25 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) Offset Bit Position 0x0EC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 46: Auxhfrcocal6 - Auxhfrco Calibration Register (13 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.26 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) Offset Bit Position 0x0F8 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 47: Auxhfrcocal7 - Auxhfrco Calibration Register (16 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.27 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) Offset Bit Position 0x0FC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 48: Auxhfrcocal8 - Auxhfrco Calibration Register (19 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.28 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) Offset Bit Position 0x100 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 49: Auxhfrcocal10 - Auxhfrco Calibration Register (26 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.29 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) Offset Bit Position 0x108 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 50: Auxhfrcocal11 - Auxhfrco Calibration Register (32 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.30 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) Offset Bit Position 0x10C Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 51: Auxhfrcocal12 - Auxhfrco Calibration Register (38 Mhz)
EFM32JG1 Reference Manual Memory and Bus System 4.7.31 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) Offset Bit Position 0x110 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Compa- rator Reference FINETUNINGEN AUXHFRCO enable reference for fine tuning... -
Page 52: Vmoncal0 - Vmon Calibration Register 0
EFM32JG1 Reference Manual Memory and Bus System 4.7.32 VMONCAL0 - VMON Calibration Register 0 Offset Bit Position 0x140 Access Name Name Access Description 31:28 ALTAVDD2V98THRESCOARSE ALTAVDD 2.98 V Coarse Threshold Adjust 27:24 ALTAVDD2V98THRESFINE ALTAVDD 2.98 V Fine Threshold Adjust 23:20 ALTAVDD1V86THRESCOARSE ALTAVDD 1.86 V Coarse Threshold Adjust... -
Page 53: Vmoncal1 - Vmon Calibration Register 1
EFM32JG1 Reference Manual Memory and Bus System 4.7.33 VMONCAL1 - VMON Calibration Register 1 Offset Bit Position 0x144 Access Name Name Access Description 31:28 IO02V98THRESCOARSE IO0 2.98 V Coarse Threshold Adjust 27:24 IO02V98THRESFINE IO0 2.98 V Fine Threshold Adjust 23:20 IO01V86THRESCOARSE IO0 1.86 V Coarse Threshold Adjust... -
Page 54: Vmoncal2 - Vmon Calibration Register 2
EFM32JG1 Reference Manual Memory and Bus System 4.7.34 VMONCAL2 - VMON Calibration Register 2 Offset Bit Position 0x148 Access Name Name Access Description 31:28 FVDD2V98THRESCOARSE FVDD 2.98 V Coarse Threshold Adjust 27:24 FVDD2V98THRESFINE FVDD 2.98 V Fine Threshold Adjust 23:20 FVDD1V86THRESCOARSE FVDD 1.86 V Coarse Threshold Adjust... -
Page 55: Idac0Cal0 - Idac0 Calibration Register 0
EFM32JG1 Reference Manual Memory and Bus System 4.7.35 IDAC0CAL0 - IDAC0 Calibration Register 0 Offset Bit Position 0x158 Access Name Name Access Description 31:24 SOURCERANGE3TUNING Calibrated middle step (16) of current source mode range 3 23:16 SOURCERANGE2TUNING Calibrated middle step (16) of current source mode... -
Page 56: Idac0Cal1 - Idac0 Calibration Register 1
EFM32JG1 Reference Manual Memory and Bus System 4.7.36 IDAC0CAL1 - IDAC0 Calibration Register 1 Offset Bit Position 0x15C Access Name Name Access Description 31:24 SINKRANGE3TUNING Calibrated middle step (16) of current sink mode range 3 23:16 SINKRANGE2TUNING Calibrated middle step (16) of current sink mode... -
Page 57: Dcdclpvctrl0 - Dcdc Low-Power Vref Trim Register 0
EFM32JG1 Reference Manual Memory and Bus System 4.7.38 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 Offset Bit Position 0x16C Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=1 23:16 1V2LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.2V output, LPATT=0,... -
Page 58: Dcdclpvctrl1 - Dcdc Low-Power Vref Trim Register 1
EFM32JG1 Reference Manual Memory and Bus System 4.7.39 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 Offset Bit Position 0x170 Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=3 23:16 1V2LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.2V output, LPATT=0,... -
Page 59: Dcdclpvctrl2 - Dcdc Low-Power Vref Trim Register 2
EFM32JG1 Reference Manual Memory and Bus System 4.7.40 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 Offset Bit Position 0x174 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=1 23:16 1V8LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=1,... -
Page 60: Dcdclpvctrl3 - Dcdc Low-Power Vref Trim Register 3
EFM32JG1 Reference Manual Memory and Bus System 4.7.41 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 Offset Bit Position 0x178 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3 23:16 1V8LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=1,... -
Page 61: Dcdclpcmphyssel1 - Dcdc Lpcmphyssel Trim Register 1
EFM32JG1 Reference Manual Memory and Bus System 4.7.43 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 Offset Bit Position 0x180 Access Name Name Access Description 31:24 LPCMPHYSSELLPCMPBIAS3 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=3 23:16 LPCMPHYSSELLPCMPBIAS2 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=2 15:8 LPCMPHYSSELLPCMPBIAS1 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=1... -
Page 62: Dbg - Debug Interface
EFM32JG1 Reference Manual DBG - Debug Interface 5. DBG - Debug Interface Quick Facts What? 0 1 2 3 The Debug Interface is used to program and debug EFM32 Jade Gecko devices. Why? The Debug Interface makes it easy to re-program and update the system in the field, and allows de- bugging with minimal I/O pin usage. -
Page 63: Debug Pins
EFM32JG1 Reference Manual DBG - Debug Interface 5.3.1 Debug Pins The following pins are the debug connections for the device: • Serial Wire Clock Input and Test Clock Input (SWCLKTCK) : This pin is enabled after reset and has a built-in pull down. -
Page 64: Debug Lock
EFM32JG1 Reference Manual DBG - Debug Interface 5.3.4 Debug Lock The debug access to the Cortex-M3 is locked by clearing the Debug Lock Word (DLW) and resetting the device, see 6.3.2 Lock Bits (LB) Page Description. When debug access is locked, the debugger can access the DAPSWJ and AAP registers. However, the connection to the Cortex-M3 core and the whole bus-system is blocked. -
Page 65: Debug Recovery
EFM32JG1 Reference Manual DBG - Debug Interface 5.3.7 Debug Recovery Debug recovery is the ability to stall the system bus before the Cortex-M3 executes code. For example, the first few instructions may disconnect the debugger pins. When this occurs it is difficult to connect the debugger and halt the Cortex-M3 before the Cortex-M3 starts to execute. -
Page 66: Aap_Cmdkey - Command Key Register
EFM32JG1 Reference Manual DBG - Debug Interface 5.5.2 AAP_CMDKEY - Command Key Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:0 WRITEKEY 0x00000000 CMD Key Register The key value must be written to this register to write enable the AAP_CMD register. -
Page 67: Aap_Ctrl - Control Register
EFM32JG1 Reference Manual DBG - Debug Interface 5.5.4 AAP_CTRL - Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 68: Aap_Crcstatus - Crc Status Register
EFM32JG1 Reference Manual DBG - Debug Interface 5.5.6 AAP_CRCSTATUS - CRC Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 69: Aap_Crcresult - Crc Result Register
EFM32JG1 Reference Manual DBG - Debug Interface 5.5.8 AAP_CRCRESULT - CRC Result Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:0 CRCRESULT 0x00000000 CRC Result of the CRCADDRESS Result of the CRC calculation using the CRCADDRESS. -
Page 70: Msc - Memory System Controller
EFM32JG1 Reference Manual MSC - Memory System Controller 6. MSC - Memory System Controller Quick Facts What? 0 1 2 3 The user can perform Flash memory read, read con- figuration and write operations through the Memory System Controller (MSC) . -
Page 71: Features
EFM32JG1 Reference Manual MSC - Memory System Controller 6.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M3 code interface • Zero wait-state access up to 32 MHz • Advanced energy optimization functionality • Conditional branch target prefetch suppression •... -
Page 72: Functional Description
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3 Functional Description The size of the main block is device dependent. The largest size available is 256 KB (128 pages). The information block has 2048 available for user data. The information block also contains chip configuration data located in a reserved area. The main block is map- ped to address 0x00000000 and the information block is mapped to address 0x0FE00000. -
Page 73: Lock Bits (Lb)
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3.2 Lock Bits (LB) Page Description This page contains the following information: • Main block Page Lock Words (PLWs) • User data page Lock Word (ULWs) • Debug Lock Word (DLW) • Mass erase Lock Word (MLW) •... -
Page 74: Device Revision
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3.5 Device Revision Family, FamilyAlt, RevMajor, RevMajorAlt, RevMinor can be accessed through ROM Table. The Revision number is extracted from the PID2 and PID3 registers, as illustrated in Figure 6.1 Revision Number Extraction on page 73.The Rev[7:4] and Rev[3:0] must be com-... -
Page 75: Wait-States
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3.8 Wait-states Table 6.4. Flash Wait-States Wait-States Frequency no more than 32 MHz above 32 MHz and no more than 40 MHz 6.3.8.1 One Wait-state Access After reset, the HFCORECLK is normally 19 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 (one wait-state). -
Page 76: Instruction Cache
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3.11 Instruction Cache The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy. -
Page 77: Erase And Write Operations
EFM32JG1 Reference Manual MSC - Memory System Controller 6.3.12 Erase and Write Operations Both page erase and write operations require that the address is written into the MSC_ADDRB register. For erase operations, the ad- dress may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register. -
Page 78: Register Map
EFM32JG1 Reference Manual MSC - Memory System Controller 6.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register... -
Page 79: Register Description
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5 Register Description 6.5.1 MSC_CTRL - Memory System Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 80: Msc_Readctrl - Read Control Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 79... - Page 81 EFM32JG1 Reference Manual MSC - Memory System Controller Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCBTP Suppress Conditional Branch Target Perfetch Enable suppressed Conditional Branch Target Prefetch (SCBTP) function. SCBTP saves energy by delaying Cortex-M4 conditional branch target prefetches until the conditional branch instruction is in the execute stage.
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Page 82: Msc_Writectrl - Write Control Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.3 MSC_WRITECTRL - Write Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 83: Msc_Writecmd - Write Command Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.4 MSC_WRITECMD - Write Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 84: Msc_Addrb - Page Erase/Write Address Buffer
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.5 MSC_ADDRB - Page Erase/Write Address Buffer Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:0 ADDRB 0x00000000 Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_CMD is set. -
Page 85: Msc_Status - Status Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.7 MSC_STATUS - Status Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 86: Msc_If - Interrupt Flag Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.8 MSC_IF - Interrupt Flag Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 87: Msc_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.9 MSC_IFS - Interrupt Flag Set Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 88: Msc_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.10 MSC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 89: Msc_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.11 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 90: Msc_Lock - Configuration Lock Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.12 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 91: Msc_Cachecmd - Flash Cache Command Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.13 MSC_CACHECMD - Flash Cache Command Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 92: Msc_Cachemisses - Cache Misses Performance Counter
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 93: Msc_Startup - Startup Control
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.17 MSC_STARTUP - Startup Control Offset Bit Position 0x05C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 94: Msc_Cmd - Command Register
EFM32JG1 Reference Manual MSC - Memory System Controller 6.5.18 MSC_CMD - Command Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 95: Ldma - Linked Dma Controller
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7. LDMA - Linked DMA Controller Quick Facts What? 0 1 2 3 The LDMA controller can move data without CPU in- tervention, effectively reducing the energy consump- tion for a data transfer. -
Page 96: Features
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.1.1 Features • Flexible Source and Destination transfers • Memory-to-memory • Memory-to-peripheral • Peripheral-to-memory • Peripheral-to-peripheral • DMA transfers triggered by peripherals, software, or linked list • Single or multiple data transfers for each peripheral or software request •... -
Page 97: Block Diagram
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.2 Block Diagram An overview of the LDMA and the modules it interacts with is shown in Figure 7.1 LDMA Block Diagram on page Cortex Interrupts LDMA Core Error Channel done Channel 0... -
Page 98: Functional Description
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3 Functional Description The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data. -
Page 99: Transfer Count
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.1.4 Transfer Count The descriptor transfer count defines how many DMA transfers to perform. The number of bytes transferred by the descripter will de- pend on both the transfer count XFERCNT and the SIZE field settings. TOTAL_BYTES = XFERCNT * SIZE 7.3.1.5 Descriptor List... -
Page 100: Byte Swap
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.1.8 Byte Swap Enabling byte swap reverses the endianess of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for transfer sizes of word and half-word. Note that linked structure reads are not byte swapped. -
Page 101: Dma Size And Source/Destination Increment Programming
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.1.9 DMA Size and Source/Destination Increment Programming The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written... - Page 102 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Memory Memory source source 0x200 0x200 First read transmit data= First read transmit data= DMA Controller FIFO DMA Controller FIFO destination destination 0x400 0x400 First write transmit data= First write transmit data=...
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Page 103: Channel Configuration
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.2 Channel Configuration Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration slots, and descriptor looping. 7.3.2.1 Address Increment/Decrement Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of dec- rementing the source and/or destination addresses after each DMA transfer. -
Page 104: Peripheral Transfer Requests
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.4.1 Peripheral Transfer Requests By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs any time the FIFO is not empty. Uppon receving an SREQ the LDMA will perform one DMA transfer and stop till another request is made. - Page 105 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Table 7.1. Arbitration Slot Order Arb- slot order Arb- slot1 Arb- slot2 Arb- slot4 Arb- slot8 The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta- tion of the arbitration order.
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Page 106: Dma Transfer Arbitration
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.6.2 DMA Transfer Arbitration In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles. -
Page 107: Channel Descriptor Data Structure
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.7 Channel descriptor data structure Each channel descriptor consists of four 32-bit words: • CTRL - control word contains information like transfer count and block size. • SRC - source address points to where to copy data from •... -
Page 108: Sync Descriptor Structure
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.7.2 SYNC descriptor structure This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continu- ing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue. -
Page 109: Wri Descriptor Structure
EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Description This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN). -
Page 110: Interrupts
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.3.9 Interrupts The LDMA_IF Interrupt flag register contains one DONE bit for each channel and one combined ERROR bit. When enabled, these in- terrupts are available as interrupts to the Cortex-M3 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM Cortex-M3 core, an interrupt will be made if one or more of the interrupt flags in LDMA_IF and their corresponding bits in LDMA_IEN are set. -
Page 111: Descriptor Linked List
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.2 Descriptor Linked List This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. - Page 112 EFM32JG1 Reference Manual LDMA - Linked DMA Controller To start execution of the linked list of descriptors: • Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register • Set the LINK bit of teh LDMA_CH0_LINK register.
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Page 113: Single Descriptor Looped Transfer
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.3 Single Descriptor Looped Transfer This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations, the transfer stops. -
Page 114: Descriptor List With Looping
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.4 Descriptor List with Looping This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and continues on with the next sequential descriptor after looping completes. -
Page 115: Simple Inter-Channel Synchronization
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.5 Simple Inter-Channel Synchronization The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA se- quence, and wait for a synchronizing event to restart it. - Page 116 EFM32JG1 Reference Manual LDMA - Linked DMA Controller SYNC[7] STRUCTTYPE=-SYNC STRUCTTYPE=XFER wait SYNCTRIG[7]=1 STRUCTTYPE=XFER C not fetched until sync_trig[7] is set STRUCTTYPE=SYNC STRUCTTYPE=XFER set SYNC[7] Time Figure 7.8. Simple Intra-channel Synchronization Example Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before loading C.
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Page 117: Copy
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.6 2D Copy The LDMA can easily perform a 2D copy using a descriptor list with looping. This set up is visualized in Figure 7.9 2D copy on page 116. For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another. - Page 118 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Because the first descriptor already transferred one row, the number of looping repeats should be the desired height minus two. There- fore, LOOPCNT should be set to HEIGHT minus two before initiating the transfer.
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Page 119: Ping-Pong
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.4.7 Ping-Pong Communication peripherals often use ping-pong buffers. Ping-pong buffers allow the CPU to process data in one buffer while a periph- eral transmits or receives data in the other buffer. Both transmit and receive ping-pong buffers are easily implemented using the LDMA. In either case, this requires two descriptors as shown in Figure 7.10 Infinite Ping-Pong Example on page... -
Page 120: Scatter-Gather
EFM32JG1 Reference Manual LDMA - Linked DMA Controller LINKLOAD bit to load the first descriptor and transmit the data. The DONIFS need not be set in each descriptor. The DMA will stop and then generate an interrupt at the completion of each descriptor. -
Page 121: Register Map
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LDMA_CTRL DMA Control Register 0x004 LDMA_STATUS DMA Status Register 0x008 LDMA_SYNC DMA Synchronization Trigger Register (Single-Cycle RMW) -
Page 122: Register Description
EFM32JG1 Reference Manual LDMA - Linked DMA Controller Offset Name Type Description 0x1E4 LDMA_CH7_DST Channel Descriptor Destination Data Address Register 0x1E8 LDMA_CH7_LINK Channel Descriptor Link Structure Address Register 7.6 Register Description 7.6.1 LDMA_CTRL - DMA Control Register Offset Bit Position... -
Page 123: Ldma_Status - Dma Status Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.2 LDMA_STATUS - DMA Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 124: Ldma_Sync - Dma Synchronization Trigger Register (Single-Cycle Rmw)
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 125: Ldma_Chbusy - Dma Channel Busy Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.5 LDMA_CHBUSY - DMA Channel Busy Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 126: Ldma_Dbghalt - Dma Channel Debug Halt Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 127: Ldma_Reqdis - Dma Channel Request Disable Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.9 LDMA_REQDIS - DMA Channel Request Disable Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 128: Ldma_Linkload - Dma Channel Link Load Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 129: Ldma_If - Interrupt Flag Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.13 LDMA_IF - Interrupt Flag Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description ERROR Transfer Error Interrupt Flag The ERRORIF flag is set when a read or write error occurs. The CHERROR field in the LDMA_STATUS register reflects the number of the channel which had the last error. -
Page 130: Ldma_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.15 LDMA_IFC - Interrupt Flag Clear Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description ERROR (R)W1 Clear ERROR Interrupt Flag Write 1 to clear the ERROR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). -
Page 131: Ldma_Chx_Reqsel - Channel Peripheral Request Select Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register Offset Bit Position 0x080 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 130... - Page 132 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 SOURCESEL 0x00 Source Select Select input source to DMA channel.
- Page 133 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 0b0000 USART1RXDATAV USART1RXDATAV REQ/SREQ 0b0001 USART1TXBL USART1TXBL REQ/SREQ 0b0010 USART1TXEMPTY USART1TXEMPTY 0b0011 USART1RXDATAV- USART1RXDATAVRIGHT REQ/SREQ RIGHT 0b0100 USART1TXBLRIGHT USART1TXBLRIGHT REQ/SREQ SOURCESEL = 0b010000 (LEUART0) 0b0000 LEUART0RXDATAV LEUART0RXDATAV 0b0001...
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Page 134: Ldma_Chx_Cfg - Channel Configuration Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.18 LDMA_CHx_CFG - Channel Configuration Register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 135: Ldma_Chx_Loop - Channel Loop Counter Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 136: Ldma_Chx_Ctrl - Channel Descriptor Control Word Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register Offset Bit Position 0x08C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 135... - Page 137 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description DSTMODE Destination Addressing Mode This field specifies the destination addressing mode of linked descriptors. After loading a linked descriptor, reading this field will indicate the destination addressing mode of the linked descriptor. Note that the first descriptor always uses absolute addressing mode.
- Page 138 EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description FOUR Increment source address by four unit data sizes after each read NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.
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Page 139: Ldma_Chx_Src - Channel Descriptor Source Data Address Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description Specifies number of unit data (words, half-words, or bytes) to transfer, as determined by the SIZE field. The value written should be one less than the desired transfer count. -
Page 140: Ldma_Chx_Dst - Channel Descriptor Destination Data Address Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:0 DSTADDR 0x00000000 Destination Data Address Writing to this register sets the destination address. Reading from this register during a DMA transfer will indicate the next destination write address. -
Page 141: Ldma_Chx_Link - Channel Descriptor Link Structure Address Register
EFM32JG1 Reference Manual LDMA - Linked DMA Controller 7.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:2 LINKADDR 0x00000000 Link Structure Address To use linking, write the address of the the first linked descriptor to this register. When a linked descriptor is loaded, it may also be linked to another descriptor. -
Page 142: Rmu - Reset Management Unit
EFM32JG1 Reference Manual RMU - Reset Management Unit 8. RMU - Reset Management Unit Quick Facts What? 0 1 2 3 The RMU ensures correct reset operation. It is re- sponsible for connecting the different reset sources to the reset lines of the EFM32 Jade Gecko. -
Page 143: Functional Description
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.3 Functional Description The RMU monitors each of the reset sources of the EFM32 Jade Gecko. If one or more reset sources go active, the RMU applies reset to the EFM32 Jade Gecko. When the reset sources go inactive the EFM32 Jade Gecko starts up. At startup the EFM32 Jade Gecko loads the stack pointer and program entry point from memory, and starts execution. -
Page 144: Reset Levels
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.3.1 Reset levels The reset sources on EFM32 Jade Gecko can be divided in two main groups; Hard resets and Soft resets. The soft resets can be configured to be either DISABLED, LIMITED, EXTENDED or FULL. The reset level for soft reset sources is configured in the xxxRMODE bitfields in RMU_CTRL. -
Page 145: Rmu_Rstcause Register
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.3.2 RMU_RSTCAUSE Register Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may investigate this register in order to determine the cause of the reset. The register is cleared upon POR and software write to RMU_CMD_RCCLR. -
Page 146: Power-On Reset (Por)
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.3.3 Power-On Reset (POR) The POR ensures that the EFM32 Jade Gecko does not start up before the supply voltage V has reached the threshold voltage VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EFM32 Jade Gecko is kept in reset state. -
Page 147: Resetn Pin Reset
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.3.5 RESETn pin Reset The pin reset on EFM32 Jade Gecko can be configured to be either hard or soft. By default, pin reset is configured as a soft reset source. To configure it as a hard reset, clear the PINRESETSOFT bit in CLW0 in the Lock bit page, see 6.3.2 Lock Bits (LB) Page... -
Page 148: Registers With Alternate Reset
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.4 Registers with alternate reset Alternate reset for registers in RMU RMU reset levels POR and hard pin reset RMU_CTRL_WDOGRMODE RMU_CTRL_LOCKUPRMODE RMU_CTRL_SYSRMODE RMU_CTRL_PINRMODE RMU_CTRL_RESETSTATE Alternate reset for registers in CMU CMU reset levels... -
Page 149: Register Map
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE Reset Cause Register 0x008 RMU_CMD Command Register 0x00C... -
Page 150: Register Description
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.6 Register Description 8.6.1 RMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 149... - Page 151 EFM32JG1 Reference Manual RMU - Reset Management Unit Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 25:24 RESETSTATE System Software Reset State Bit-field for software use only. This field has no effect on the RMU and is reset by power-on reset and hard pin reset only.
- Page 152 EFM32JG1 Reference Manual RMU - Reset Management Unit Name Reset Access Description DISABLED Reset request is blocked. This disable bit is redundant with enable/ disable bit in WDOG LIMITED The CRYOTIMER, DEBUGGER, RTCC, are not reset. EXTENDED The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.
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Page 153: Rmu_Rstcause - Reset Cause Register
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.6.2 RMU_RSTCAUSE - Reset Cause Register Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 152... - Page 154 EFM32JG1 Reference Manual RMU - Reset Management Unit Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4RST EM4 Reset Set if the system has been in EM4. Must be cleared by software. Please see Table 8.2 RMU Reset Cause Register Inter-...
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Page 155: Rmu_Cmd - Command Register
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.6.3 RMU_CMD - Command Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 156: Rmu_Lock - Configuration Lock Register
EFM32JG1 Reference Manual RMU - Reset Management Unit 8.6.5 RMU_LOCK - Configuration Lock Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 157: Emu - Energy Management Unit
EFM32JG1 Reference Manual EMU - Energy Management Unit 9. EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in EFM32 Jade Gecko Why? The need for performance and peripheral functions varies over time in most applications. -
Page 158: Functional Description
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3 Functional Description The EMU is responsible for managing the wide range of energy modes available in EFM32 Jade Gecko. The block works in harmony with the entire platform to easily transition between energy modes in the most efficient manner possible. The following diagram Figure 9.1 EMU Overview on page... -
Page 159: Energy Modes
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.1 Energy Modes EFM32 Jade Gecko features six main energy modes, referred to as Energy Mode 0 (EM0 Active) through Energy Mode 4 (EM4 Shut- off). The Cortex-M3 is only available for program execution in EM0 Active. In EM0 Active/EM1 Sleep any peripheral function can be enabled. -
Page 160: Em0 Active
EFM32JG1 Reference Manual EMU - Energy Management Unit EM0 Active EM1 Sleep EM2 Deep- EM3 Stop EM4 Hiber- EM4 Shutoff Sleep nate LEUART (Low Energy UART) Available Available Available Available Available Available Available ACMP (Analog Comparator) Available Available Available Available... -
Page 161: Em2 Deepsleep
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.1.3 EM2 DeepSleep This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionali- ty. Memory and registers retain their values. -
Page 162: Em4 Shutoff
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.1.6 EM4 Shutoff EM4 Shutoff is the lowest energy mode of the part. There is no retention except for GPIO PAD state. Wakeup from EM4 Shutoff re- quires a reset to the system, returning it back to EM0 Active •... -
Page 163: Exiting A Low Energy Mode
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.3 Exiting a Low Energy Mode A system in EM2 DeepSleep and EM3 Stop can be woken up to EM0 Active through regular interrupt requests from active peripherals. Since state and RAM retention is available, the EFM32 is fully restored and can continue to operate as before it went into the Low Energy Mode. -
Page 164: Power Configurations
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.4 Power Configurations The EFM32 Jade Gecko allows several power configurations with additional options giving flexible power architecture selection. In order to provide the lowest power consuming solutions, the EFM32 Jade Gecko comes with a DC-DC module to power internal cir- cuits. -
Page 165: Power Configuration 0: Startup
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.4.1 Power Configuration 0: STARTUP During power-on reset (POR), the system boots up in a safe Startup Configuration that supports all of the available Power Configura- tions. The Startup Configuration is shown in the simplified diagram below. -
Page 166: Power Configuration 1: No Dc-Dc
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.4.2 Power Configuration 1: No DC-DC In Power Configuration 1, the DC-DC converter is programmed in Off mode and the Bypass switch is Off. The DVDD pin must be pow- ered externally - typically, DVDD is connected to the main supply. IOVDD and AVDD are powered from the main supply as well. -
Page 167: Power Configuration 2: Dc-Dc
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.4.3 Power Configuration 2: DC-DC For the lowest power applications, the DC-DC converter can be used to power the DVDD supply. In Power Configuration 2, the DC-DC Output (V ) is connected to DVDD. DVDD powers the internal Digital LDO which powers the DCDC digital circuits. -
Page 168: Bypass Mode
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.5.1 Bypass Mode In Bypass mode, the VREGVDD input voltage is directly shorted to the DC-DC converter output through an internal switch. Out of reset, the DC-DC converter defaults to Bypass mode. -
Page 169: Analog Peripheral Power Selection
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.5.4 Analog Peripheral Power Selection The analog peripherals (e.g., ULFRCO, LFRCO, LFXO, HFRCO, AUXHFRCO, VMON, IDAC, ADC) may be powered from one of two supply pins, depending on the configuration of the ANASW bit in the EMU_PWRCTRL register: Changes to the ANASW setting should be made immediately out of reset (i.e., in the Startup Configuration) before all clocks (with the exception of HFRCO and ULFRCO) are... -
Page 170: Voltage Monitor (Vmon)
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.3.7 Voltage Monitor (VMON) The EFM32 features an extremely low energy Voltage Monitor (VMON) capable of running down to EM4 Hibernate. Trigger points are preloaded but may be reconfigured. • AVDD X 2 •... -
Page 171: Register Map
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x004 EMU_STATUS Status Register 0x008 EMU_LOCK Configuration Lock Register 0x00C... -
Page 172: Register Description
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5 Register Description 9.5.1 EMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 173: Emu_Status - Status Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.2 EMU_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 174: Emu_Lock - Configuration Lock Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.3 EMU_LOCK - Configuration Lock Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 175: Emu_Ram0Ctrl - Memory Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.4 EMU_RAM0CTRL - Memory Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 176: Emu_Cmd - Command Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.5 EMU_CMD - Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 177: Emu_Em4Ctrl - Em4 Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.6 EMU_EM4CTRL - EM4 Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 178: Emu_Templimits - Temperature Limits For Interrupt Generation
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.7 EMU_TEMPLIMITS - Temperature limits for interrupt generation Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 179: Emu_If - Interrupt Flag Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.9 EMU_IF - Interrupt Flag Register Offset Bit Position 0x024 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 178... - Page 180 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description TEMPHIGH Temperature High Limit Reached Set when the value of a periodic temperature measurement is higher or equal than TEMPHIGH in EMU_TEMPLIMITS TEMPLOW Temperature Low Limit Reached Set when the value of a periodic temperature measurement is lower or equal than TEMPHIGH in EMU_TEMPLIMITS...
- Page 181 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description A rising edge on Alternate VMON AVDD channel has been detected. VMONALTAVDDFALL 0 Alternate VMON AVDD Channel Fall A falling edge on Alternate VMON AVDD channel has been detected.
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Page 182: Emu_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.10 EMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x028 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 181... - Page 183 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description TEMPHIGH Set TEMPHIGH Interrupt Flag Write 1 to set the TEMPHIGH interrupt flag TEMPLOW Set TEMPLOW Interrupt Flag Write 1 to set the TEMPLOW interrupt flag TEMP Set TEMP Interrupt Flag...
- Page 184 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONDVDDFALL Set VMONDVDDFALL Interrupt Flag Write 1 to set the VMONDVDDFALL interrupt flag VMONALTAVDDRISE 0 Set VMONALTAVDDRISE Interrupt Flag Write 1 to set the VMONALTAVDDRISE interrupt flag VMONALTAVDDFALL 0...
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Page 185: Emu_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.11 EMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x02C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 184... - Page 186 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description TEMPHIGH (R)W1 Clear TEMPHIGH Interrupt Flag Write 1 to clear the TEMPHIGH interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 187 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description 11:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions VMONIO0RISE (R)W1 Clear VMONIO0RISE Interrupt Flag Write 1 to clear the VMONIO0RISE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 188: Emu_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.12 EMU_IEN - Interrupt Enable Register Offset Bit Position 0x030 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 187... - Page 189 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description TEMPHIGH TEMPHIGH Interrupt Enable Enable/disable the TEMPHIGH interrupt TEMPLOW TEMPLOW Interrupt Enable Enable/disable the TEMPLOW interrupt TEMP TEMP Interrupt Enable Enable/disable the TEMP interrupt 28:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 190: Emu_Pwrlock - Regulator And Supply Lock Register
EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONDVDDFALL VMONDVDDFALL Interrupt Enable Enable/disable the VMONDVDDFALL interrupt VMONALTAVDDRISE 0 VMONALTAVDDRISE Interrupt Enable Enable/disable the VMONALTAVDDRISE interrupt VMONALTAVDDFALL 0 VMONALTAVDDFALL Interrupt Enable Enable/disable the VMONALTAVDDFALL interrupt VMONAVDDRISE VMONAVDDRISE Interrupt Enable... -
Page 191: Emu_Pwrcfg - Power Configuration Register. This Is No Longer Used
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.14 EMU_PWRCFG - Power Configuration Register. This is no longer used Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 192: Emu_Dcdcctrl - Dcdc Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.16 EMU_DCDCCTRL - DCDC Control Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 193: Emu_Dcdcmiscctrl - Dcdc Miscellaneous Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.17 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register Offset Bit Position 0x04C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 192... - Page 194 EFM32JG1 Reference Manual EMU - Energy Management Unit Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28 LPCMPBIAS LP mode comparator bias selection LP mode comparator bias selection. Reset with POR, Hard Pin Reset, or BOD Reset.
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Page 195: Emu_Dcdczdetctrl - Dcdc Power Train Nfet Zero Current Detector Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.18 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 196: Emu_Dcdcclimctrl - Dcdc Power Train Pfet Current Limiter Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.19 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 197: Emu_Dcdclnvctrl - Dcdc Low Noise Voltage Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 198: Emu_Dcdctiming - Dcdc Controller Timing Value Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.21 EMU_DCDCTIMING - DCDC Controller Timing Value Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 199: Emu_Dcdclpvctrl - Dcdc Low Power Voltage Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.22 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 200: Emu_Dcdclpctrl - Dcdc Low Power Control Register
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.23 EMU_DCDCLPCTRL - DCDC Low Power Control Register Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 201: Emu_Dcdclnfreqctrl - Dcdc Low Noise Controller Frequency Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.24 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 202: Emu_Vmonavddctrl - Vmon Avdd Channel Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.26 EMU_VMONAVDDCTRL - VMON AVDD Channel Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 203: Emu_Vmonaltavddctrl - Alternate Vmon Avdd Channel Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.27 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 204: Emu_Vmondvddctrl - Vmon Dvdd Channel Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.28 EMU_VMONDVDDCTRL - VMON DVDD Channel Control Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 205: Emu_Vmonio0Ctrl - Vmon Iovdd0 Channel Control
EFM32JG1 Reference Manual EMU - Energy Management Unit 9.5.29 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 206: Cmu - Clock Management Unit
EFM32JG1 Reference Manual CMU - Clock Management Unit 10. CMU - Clock Management Unit Quick Facts What? 0 1 2 3 The CMU controls oscillators and clocks. EFM32 Jade Gecko supports 6 different oscillators with minimized power consumption and short start-up time. -
Page 207: Functional Description
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3 Functional Description An overview of the high frequency portion of CMU is shown in Figure 10.1 CMU Overview - High Frequency Portion on page 206. An overview of the low frequency portion is shown in Figure 10.2 CMU Overview - Low Frequency Portion on page... -
Page 208: System Clocks
EFM32JG1 Reference Manual CMU - Clock Management Unit HFPERCLK ADCn CMU_ADCCTRL.ADCCLKINV ADC_CLK HFSRCCLK HFXO ADCCLKMODE CMU_ADCCTRL.ADCCLKSEL AUXCLK Timeout (Flash Programming) HFRCO CMU_DBGCLKSEL.DBG clock DBGCLK Debug Trace switch CMU_HFPRESC.PRESC HFXO Timeout HFSRCCLK clock prescaler switch Timeout CMU_HFPERCLKEN0.TIMER0 Clock HFPERCLK HFCLK TIMER0... -
Page 209: Hfclk - High Frequency Clock
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.1.1 HFCLK - High Frequency Clock HFSRCCLK is the selected High Frequency Source Clock. HFCLK is an optionally prescaled version of HFSRCCLK. The HFSRCCLK, and therefore HFCLK, can be driven by a high-frequency oscillator (HFRCO or HFXO or HFRCODIV2 see ) or one of the low-frequency oscillators (LFRCO or LFXO). -
Page 210: Lfaclk - Low Frequency A Clock
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.1.5 LFACLK - Low Frequency A Clock LFACLK is the selected clock for the Low Energy A Peripherals. There are three selectable sources for LFACLK: LFRCO, LFXO and ULFRCO. In addition, the LFACLK can be disabled, which is the default setting. The selection is configured using the LFA field in CMU_LFACLKSEL. -
Page 211: Auxclk - Auxiliary Clock
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.1.11 AUXCLK - Auxiliary Clock AUXCLK is a 1 MHz - 38 MHz clock driven by a separate RC oscillator, the AUXHFRCO. This clock can be used for ADC operation and Serial Wire Output (SWO). When the AUXHFRCO is selected as the ADC clock via the ADC0CLKSEL bitfield in the CMU_ADCCTRL register this clock will become active automatically when needed. -
Page 212: Enabling And Disabling
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.1 Enabling and Disabling The different oscillators can typically be enabled and disabled via both hardware and software mechanisms. Enabling via software is done by setting the corresponding enable bit in the CMU_OSCENCMD register. Disabling via software is done by setting the corre- sponding disable bit in CMU_OSCENCMD. - Page 213 EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.1.1 LFRCO and LFXO The LFXO and LFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The WDOG can be configured to force the LFXO or LFRCO to become (and remain) enabled when such an oscillator is selected as its clock source via the CLKSEL bitfield in the WDOG_CTRL register while SWOSCBLOCK is set.
- Page 214 EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.1.4 HFXO The HFXO can be enabled and disabled by software via the CMU_OSCENCMD register. The HFXO is disabled automatically when entering EM2, EM3, or EM4. Hardware based HFXO enabling can be initiated by various peripherals as configured via the AUTOSTAR- TEM0EM1, AUTOSTARTSELEM0EM1 bits in the CMU_HFXOCTRL register.
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Page 215: Oscillator Start-Up Time And Time-Out
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.2 Oscillator Start-up Time and Time-out The start-up time differs per oscillator and the usage of an oscillator clock can further be delayed by a time-out. The LFRCO, LFXO and the HFXO have a configurable time-out which is set by software in the (various) TIMEOUT bitfields of the CMU_LFRCOCTRL, CMU_LFXOCTRL and CMU_HFXOTIMEOUTCTRL registers respectively. -
Page 216: Switching Clock Source
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.3 Switching Clock Source The HFRCO oscillator is a low energy oscillator with extremely short start-up time. Therefore, this oscillator is always chosen by hard- ware as the clock source for HFCLK when the device starts up (e.g. after reset and after waking up from EM2 DeepSleep and EM3 Stop). - Page 217 EFM32JG1 Reference Manual CMU - Clock Management Unit CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO HFXO time-out period Figure 10.5. CMU Switching from HFRCO to HFXO after HFXO is ready Switching clock source for LFACLK, LFBCLK, and LFECLK is done by setting the LFA, LFB and LFE bitfields in CMU_LFACLKSEL, CMU_LFBCLKSEL, and CMU_LFECLKSEL respectively.
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Page 218: Hfxo Configuration
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.4 HFXO Configuration The High Frequency Crystal Oscillator needs to be configured to ensure safe startup for the given crystal. Refer to the Device Data- sheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs. - Page 219 EFM32JG1 Reference Manual CMU - Clock Management Unit Reset || EM2/EM3 entry || (CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS) HFXO major mode configuration from CMU->HFXOCTRL: · MODE · LOWPOWER Startup state configuration from CMU->HFXOSTARTUPCTRL: · IBTRIMXOCORE · CTUNE · REGISH · LOWPOWER CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN Timeout configuration from CMU->HFXOTIMEOUTCTRL:...
- Page 220 EFM32JG1 Reference Manual CMU - Clock Management Unit Refer to the Device Datasheet to find the configuration values for a given crystal. The startup state configuration needs to be written into the IBTRIMXOCORE and CTUNE bitfields of the CMU_HFXOSTARTUPCTRL register. The duration of the startup phase is config- ured in the STARTUPTIMEOUT bitfield of the CMU_HFXOTIMEOUTCTRL register.
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Page 221: Lfxo Configuration
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.5 LFXO Configuration The Low Frequency Crystal Oscillator (LFXO) is default configured to ensure safe startup for all crystals. In order to optimize startup time and power consumption for a given crystal, it is possible to adjust the startup gain in the oscillator by programming the GAIN field in CMU_LFXOCTRL. -
Page 222: Hfrco And Auxhfrco Configuration
EFM32JG1 Reference Manual CMU - Clock Management Unit The AGC bit of the CMU_LFXOCTRL register is used to turn on or off the Automatic Gain Control module that adjusts the amplitude of the XTAL. When disabled, the LFXO will run at the startup current and the XTAL will oscillate rail to rail, again providing safer operation, improved duty cycle, and lower sensitivity to noise at the cost of increased current consumption. -
Page 223: Rc Oscillator Calibration
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.8 RC Oscillator Calibration The CMU has built-in HW support to efficiently calibrate the RC oscillators (LFRCO, HFRCO, AUXHFRCO) at run-time, see Figure 10.10 HW-support for RC Oscillator Calibration on page 222 for an illustration of this circuit. - Page 224 EFM32JG1 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt flag set. Sampled value available in CMU_CALCNT. Up-counter Down-counter Calibration Started Calibration Stopped (counters stopped) Figure 10.11. Single Calibration (CONT=0) Up-counter sampled and CALRDY Up-counter sampled and CALRDY interrupt flag set.
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Page 225: Automatic Hfxo Start
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.2.9 Automatic HFXO Start The enabling of the HFXO and its selection as HFCLKSRC source can be performed automatically by hardware. Automatic control of the HFXO is controlled via the AUTOSTARTSELEM0EM1 and AUTOSTARTEM0EM1 bits in the CMU_HFXOCTRL register. It further depends on the energy mode of the EFM32 . - Page 226 EFM32JG1 Reference Manual CMU - Clock Management Unit The interaction between automatic HFXO startup and selection with startup and selection of HFRCO is shown in Figure 10.14 CMU HFRCO startup/selection while awaiting automatic HFXO startup/selection on page 225. EM0/EM1 Entry &&...
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Page 227: Configuration For Operating Frequencies
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.3 Configuration For Operating Frequencies The HFXO is capable of driving crystals up to 40 MHz, which allows the EFM32 to run at up to this frequency. However, the Memory System Controller (MSC) and the Low Energy Peripheral Interface need to be configured correctly to allow operation at higher frequen- cies as explained below. -
Page 228: Energy Modes
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.4 Energy Modes The availability of oscillators and system clocks depends on the chosen energy mode. Default the high frequency oscillators (HFRCO, AUXHFRCO, and HFXO) and high frequency clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFCLKLE) are available downto EM1 Sleep. -
Page 229: Clock Output On A Pin
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.5 Clock Output on a Pin It is possible to configure the CMU to output clocks on the CMU_CLK0 and CMU_CLK1 pins. This clock selection is done using the CLKOUTSEL0 and CLKOUTSEL1 bitfields respectively in CMU_CTRL. The required output pins must be enabled in the CMU_ROU- TEPEN register and the pin locations can be configured in the CMU_ROUTELOC0 register. -
Page 230: Wake-Up
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.3.10 Wake-up The CMU can be (partially) active all the way down to EM4 Shutoff. It can wake up the CPU from EM2 upon LFRCO or LFXO becoming ready as LFRCORDY and LFXORDY can be used as wake-up interrupt. -
Page 231: Register Map
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x010 CMU_HFRCOCTRL HFRCO Control Register 0x018 CMU_AUXHFRCOCTRL AUXHFRCO Control Register... - Page 232 EFM32JG1 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x120 CMU_LFAPRESC0 Low Frequency A Prescaler Register 0 (Async Reg) 0x128 CMU_LFBPRESC0 Low Frequency B Prescaler Register 0 (Async Reg) 0x130 CMU_LFEPRESC0 Low Frequency E Prescaler Register 0 (Async Reg). When waking up...
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Page 233: Register Description
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5 Register Description 10.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 232... - Page 234 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFPERCLKEN HFPERCLK Enable Set to enable the HFPERCLK. 19:17 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 235 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFRCOQ LFRCO (qualified) LFXOQ LFXO (qualified) HFRCOQ HFRCO (qualified) AUXHFRCOQ AUXHFRCO (qualified) HFXOQ HFXO (qualified) HFSRCCLK HFSRCCLK silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 234...
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Page 236: Cmu_Hfrcoctrl - Hfrco Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.2 CMU_HFRCOCTRL - HFRCO Control Register Write this register to set the frequency band in which the HFRCO is to operate. Always update all fields in this registers at once by writing the value for the desired band, which has been obtained from the Device Information page entry for that band. The TUNING, FINETUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non- preconfigured frequency. - Page 237 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference Writing this field adjusts the temperature coefficient trim on comparator reference. FINETUNINGEN Enable reference for fine tuning Settings this bit enables HFRCO fine tuning.
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Page 238: Cmu_Auxhfrcoctrl - Auxhfrco Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Write this register with the production calibrated values from the Device Info pages. The TUNING, FINETUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-preconfigured frequency. Only write CMU_AUXHFRCOCTRL when it is ready for an update as indicated by AUXHFRCOBSY=0 in CMU_SYNCBUSY. -
Page 239: Cmu_Lfrcoctrl - Lfrco Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.4 CMU_LFRCOCTRL - LFRCO Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:28 GMCCURTUNE Tuning of gmc current Set to tune GMC current. This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices. -
Page 240: Cmu_Hfxoctrl - Hfxo Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.5 CMU_HFXOCTRL - HFXO Control Register Offset Bit Position 0x024 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 239... - Page 241 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions AUTOSTARTSE- Automatically start and select of HFXO upon EM0/EM1 entry from...
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Page 242: Cmu_Hfxoctrl1 - Hfxo Control 1
EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can be used to trigger peak detection and shunt optimization sequences. MANUAL CMU_HFXOSTEADYSTATECTRL IBTRIMXOCORE, REGISH, RE- GSELILOW, and PEAKDETEN are under full software control and are allowed to be changed once HFXO is ready. -
Page 243: Cmu_Hfxostartupctrl - Hfxo Startup Control
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.7 CMU_HFXOSTARTUPCTRL - HFXO Startup Control Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:28 RESERVED1 Sets the regulator output current level (shunt regulator). Ish=120uA+reg_ish x 120uA This REGISH value is applied during the keep warm phase of the HFXO... -
Page 244: Cmu_Hfxosteadystatectrl - Hfxo Steady State Control
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.8 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:28 REGISHUPPER Set regulator output current level (shunt regulator). Ish = 120uA + REGISHUPPER x 120uA Set to steady state value of REGISH + 3. -
Page 245: Cmu_Hfxotimeoutctrl - Hfxo Timeout Control
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control Offset Bit Position 0x034 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 244... - Page 246 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16 SHUNTOPTTIME- Wait duration in HFXO shunt current optimization wait state Wait duration depends on the chosen XTAL (expected value is around 1 us).
- Page 247 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description Value Mode Description 2CYCLES Timeout period of 2 cycles 4CYCLES Timeout period of 4 cycles 16CYCLES Timeout period of 16 cycles 32CYCLES Timeout period of 32 cycles 256CYCLES...
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Page 248: Cmu_Lfxoctrl - Lfxo Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.10 CMU_LFXOCTRL - LFXO Control Register Offset Bit Position 0x038 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 247... - Page 249 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:24 TIMEOUT LFXO Timeout Configures the start-up delay for LFXO. Do not change while LFXO is enabled. When starting up the LFXO after it has been completely turned off, use the TIMEOUT setting required by the XTAL.
- Page 250 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description BUFEXTCLK An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32768 Hz). DIGEXTCLK Digital external clock on LFXTAL_N pin. Oscillator is effectively by- passed.
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Page 251: Cmu_Calctrl - Calibration Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.11 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x050 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 250... - Page 252 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:24 PRSDOWNSEL PRS Select for PRS Input when selected in DOWNSEL Select PRS input for PRS based calibration.
- Page 253 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description Set this bit to enable continuous calibration Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DOWNSEL Calibration Down-counter Select Selects clock source for the calibration down-counter.
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Page 254: Cmu_Calcnt - Calibration Counter Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.12 CMU_CALCNT - Calibration Counter Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 255: Cmu_Oscencmd - Oscillator Enable/Disable Command Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.13 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 256: Cmu_Cmd - Command Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.14 CMU_CMD - Command Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 257: Cmu_Dbgclksel - Debug Trace Clock Select
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.15 CMU_DBGCLKSEL - Debug Trace Clock Select Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 258: Cmu_Lfaclksel - Low Frequency A Clock Select Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.17 CMU_LFACLKSEL - Low Frequency A Clock Select Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 259: Cmu_Lfeclksel - Low Frequency E Clock Select Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.19 CMU_LFECLKSEL - Low Frequency E Clock Select Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 260: Cmu_Status - Status Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.20 CMU_STATUS - Status Register Offset Bit Position 0x090 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 259... - Page 261 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFXOREGILOW HFXO regulator shunt current too low HFXO regulator shunt current too low. When using PEAKDETSHUNTOPTMODE=MANUAL, the REGISH value in CMU_HFXOSTEADYSTATECTRL should be tuned up by 1 LSB.
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Page 262: Cmu_Hfclkstatus - Hfclk Status Register
EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFRCO is enabled. 10.5.21 CMU_HFCLKSTATUS - HFCLK Status Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 263: Cmu_Hfxotrimstatus - Hfxo Trim Status
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.22 CMU_HFXOTRIMSTATUS - HFXO Trim Status Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 264: Cmu_If - Interrupt Flag Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.23 CMU_IF - Interrupt Flag Register Offset Bit Position 0x0A0 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 263... - Page 265 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMUERR CMU Error Interrupt Flag Set upon illegal CMU write attempt (e.g. writing CMU_LFRCOCTRL while LFRCOBSY is set). 30:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 266: Cmu_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.24 CMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x0A4 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 265... - Page 267 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMUERR Set CMUERR Interrupt Flag Write 1 to set the CMUERR interrupt flag 30:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 268: Cmu_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.25 CMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x0A8 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 267... - Page 269 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMUERR (R)W1 Clear CMUERR Interrupt Flag Write 1 to clear the CMUERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 270 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFXORDY (R)W1 Clear HFXORDY Interrupt Flag Write 1 to clear the HFXORDY interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 271: Cmu_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.26 CMU_IEN - Interrupt Enable Register Offset Bit Position 0x0AC Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 270... - Page 272 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMUERR CMUERR Interrupt Enable Enable/disable the CMUERR interrupt 30:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFTIMEOUTERR...
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Page 273: Cmu_Hfbusclken0 - High Frequency Bus Clock Enable Register 0
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.27 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 274: Cmu_Hfperclken0 - High Frequency Peripheral Clock Enable Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.28 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 275: Cmu_Lfaclken0 - Low Frequency A Clock Enable Register 0 (Async Reg)
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.29 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) Offset Bit Position 0x0E0 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 276: Cmu_Lfeclken0 - Low Frequency E Clock Enable Register 0 (Async Reg)
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.31 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) Offset Bit Position 0x0F0 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 277: Cmu_Hfpresc - High Frequency Clock Prescaler Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 278: Cmu_Hfcorepresc - High Frequency Core Clock Prescaler Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.33 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 279: Cmu_Hfexppresc - High Frequency Export Clock Prescaler Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.35 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register Offset Bit Position 0x114 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 280: Cmu_Lfapresc0 - Low Frequency A Prescaler Register 0 (Async Reg)
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.36 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 281: Cmu_Lfbpresc0 - Low Frequency B Prescaler Register 0 (Async Reg)
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.37 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 282: Cmu_Syncbusy - Synchronization Busy Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.39 CMU_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x140 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 281... - Page 283 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXOBSY LFXO Busy Used to check the synchronization status of CMU_LFXOCTRL.
- Page 284 EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMU_HFRCOCTRL is ready for update CMU_HFRCOCTRL is busy synchronizing new value 23:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 285: Cmu_Freeze - Freeze Register
EFM32JG1 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMU_LFAPRESC0 is busy synchronizing new value Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFACLKEN0 Low Frequency A Clock Enable 0 Busy Used to check the synchronization status of CMU_LFACLKEN0. -
Page 286: Cmu_Pcntctrl - Pcnt Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.41 CMU_PCNTCTRL - PCNT Control Register Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 287: Cmu_Adcctrl - Adc Control Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.42 CMU_ADCCTRL - ADC Control Register Offset Bit Position 0x15C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 288: Cmu_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.43 CMU_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 289: Cmu_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.44 CMU_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x174 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 290: Cmu_Lock - Configuration Lock Register
EFM32JG1 Reference Manual CMU - Clock Management Unit 10.5.45 CMU_LOCK - Configuration Lock Register Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 291: Rtcc - Real Time Counter And Calendar
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11. RTCC - Real Time Counter and Calendar Quick Facts What? The Real Time Counter and Calendar (RTCC) is a 32-bit counter ensuring timekeeping in low energy 0 1 2 3 4 modes. -
Page 292: Features
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.2 Features • 32-bit Real Time Counter. • 15-bit pre-counter, for flexible frequency scaling or for use as an independent counter. • EM4H operation and wakeup. • 128 byte general purpose retention data. -
Page 293: Counter
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.3.1 Counter The RTCC consists of two counters; the 32-bit main counter, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode), and a 15- bit pre-counter, RTCC_PRECNT. The pre-counter can be used as an independent counter, or to generate a specific frequency for the main counter. -
Page 294: Normal Mode
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.3.1.1 Normal Mode The main counter can receive a tick based on different tappings from the pre-counter, allowing the ticks to be power of 2 divisions of the LFCLK . For more accurate configuration of the tick frequency, RTCC_CC0_CCV[14:0] can be used as a top value for RTCC RTCC_PRECNT. -
Page 295: Calendar Mode
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.3.1.2 Calendar Mode The RTCC includes a calendar mode which implements time and date decoding in hardware. Calendar mode is enabled by configuring CNTMODE in RTCC_CTRL to CALENDAR. When in calendar mode, the counter value is available in RTCC_TIME and RTCC_DATE. -
Page 296: Capture/Compare Channels
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.3.2 Capture/Compare Channels Three capture/compare channels are available in the RTCC. Each channel can be configured as input capture or output compare, by setting the corresponding MODE in the RTCC_CCx_CTRL register. - Page 297 EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar RTCC_CCx_CTRL_COMPBASE = CNT PRECNT MASK Compare match MASK CCx_CCV RTCC_CCx_CTRL_COMPBASE = PRECNT 0 14 PRECNT MASK Compare match MASK CCx_CCV Figure 11.4. RTCC Compare base illustration Table 11.3 RTCC Capture/Compare subjects on page 296 summarizes which registers being subject to comparison for different config- urations of RTCC_CTRL_CNTMODE and RTCC_CCx_CTRL_COMPBASE.
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Page 298: Interrupts And Prs Output
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar RTCC_DATE RTCC_TIME [0b000, [DAYOMT, DAYOW] DAYOMU] RTCC_CCx_CTRL_DAYCC [MONTHT,MONTHU] MASK Compare match MASK [MONTHT,MONTHU] [DAYT,DAYU] RTCC_CCx_DATE RTCC_CCx_TIME Figure 11.5. RTCC Compare in calendar mode, COMPBASE = CNT To generate periodically recurring events, is possible to mask out parts of the compare match values. By configuring COMPMASK in RTCC_CCx_CTRL, parts of the compare values will be masked out, limiting which part of the compare register being subject to com- parison with the counter. -
Page 299: Main Counter Tick Prs Output
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.3.3.1 Main Counter Tick PRS Output To output the ticks for the main counter on PRS, it is possible to use a Capture/Compare channel and mask all the bits, i.e. -
Page 300: Register Map
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTCC_CTRL Control Register 0x004 RTCC_PRECNT Pre-Counter Value Register 0x008 RTCC_CNT Counter Value Register... -
Page 301: Register Description
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5 Register Description 11.5.1 RTCC_CTRL - Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset... - Page 302 EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LYEARCORRDIS Leap year correction disabled. When cleared, February has 29 days in leap years. When set, February always has 28 days.
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Page 303: Rtcc_Precnt - Pre-Counter Value Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description DIV16384 = LFECLK /16384 RTCC DIV32768 = LFECLK /32768 RTCC Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 304: Rtcc_Cnt - Counter Value Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.3 RTCC_CNT - Counter Value Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x008 Reset Access Name... -
Page 305: Rtcc_Time - Time Of Day Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.5 RTCC_TIME - Time of day register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x010 Reset Access... -
Page 306: Rtcc_Date - Date Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.6 RTCC_DATE - Date register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name... -
Page 307: Rtcc_If - Rtcc Interrupt Flags
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.7 RTCC_IF - RTCC Interrupt Flags Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 308: Rtcc_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.8 RTCC_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 309: Rtcc_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.9 RTCC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 308... - Page 310 EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK (R)W1 Clear MONTHTICK Interrupt Flag Write 1 to clear the MONTHTICK interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 311: Rtcc_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.10 RTCC_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 312: Rtcc_Status - Status Register
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.11 RTCC_STATUS - Status register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 313: Rtcc_Powerdown - Retention Ram Power-Down Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.14 RTCC_POWERDOWN - Retention RAM power-down register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x034 Reset Access... -
Page 314: Rtcc_Em4Wuen - Wake Up Enable
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.16 RTCC_EM4WUEN - Wake Up Enable Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 315: Rtcc_Ccx_Ctrl - Cc Channel Control Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x040 Reset Access Name silabs.com | Smart. - Page 316 EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DAYCC Day Capture/Compare selection Select whether day of week, or day of month is subject for Capture/Compare.
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Page 317: Rtcc_Ccx_Ccv - Capture/Compare Value Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description FALLING Falling edges detected BOTH Both edges detected NONE No edge detection, signal is left as it is CMOA Compare Match Output Action Select output action on compare match. -
Page 318: Rtcc_Ccx_Time - Capture/Compare Time Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x048 Reset Access Name... -
Page 319: Rtcc_Ccx_Date - Capture/Compare Date Register (Async Reg)
EFM32JG1 Reference Manual RTCC - Real Time Counter and Calendar 11.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x04C Reset Access Name... -
Page 320: Wdog - Watchdog Timer
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12. WDOG - Watchdog Timer Quick Facts What? 0 1 2 3 The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available. -
Page 321: Clock Source
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOGn_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOGn_CTRL can be written to prevent accidental disabling of the selected clocks. -
Page 322: Window Interrupt
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.3.6 Window Interrupt This interrupt occurs when the watchdog is cleared below a certain threshold. This threshold is given by the formula: 3+PERSEL = (2 ) * (WINSEL/8) + 1)/f, WARNING where f is the frequency of the selected clock. -
Page 323: Prs As Watchdog Clear
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.3.7 PRS as Watchdog Clear The first PRS channel (selected by register WDOGn_PCH0_PRSCTRL) can be used to clear the watchdog counter. To enable this fea- ture, CLRSRC must be set to 1. Figure 12.2 PRS Clearing WDOG on page 322 shows how the PRS channel takes over the wdog clear function. -
Page 324: Register Map
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 0x00C WDOGn_PCH0_PRSCTRL... -
Page 325: Register Description
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. - Page 326 EFM32JG1 Reference Manual WDOG - Watchdog Timer Name Reset Access Description WDOGRSTDIS Watchdog Reset Disable Disable watchdog reset output. Value Mode Description A timeout will cause a watchdog reset A timeout will not cause a watchdog reset CLRSRC Watchdog Clear Source Select watchdog clear source.
- Page 327 EFM32JG1 Reference Manual WDOG - Watchdog Timer Name Reset Access Description Value Mode Description ULFRCO ULFRCO LFRCO LFRCO LFXO LFXO 11:8 PERSEL Watchdog Timeout Period Select Select watchdog timeout period. Value Description Timeout period of 9 watchdog clock cycles. Timeout period of 17 watchdog clock cycles.
- Page 328 EFM32JG1 Reference Manual WDOG - Watchdog Timer Name Reset Access Description LOCK Configuration lock Set to lock the watchdog configuration. This bit can only be cleared by reset. Value Description Watchdog configuration can be changed. Watchdog configuration cannot be changed.
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Page 329: Wdog_Cmd - Command Register (Async Reg)
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.2 WDOG_CMD - Command Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description... -
Page 330: Wdogn_Pchx_Prsctrl - Prs Control Register (Async Reg)
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access... -
Page 331: Wdog_If - Watchdog Interrupt Flags
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.5 WDOG_IF - Watchdog Interrupt Flags Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 332: Wdog_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.6 WDOG_IFS - Interrupt Flag Set Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 333: Wdog_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.7 WDOG_IFC - Interrupt Flag Clear Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 334: Wdog_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual WDOG - Watchdog Timer 12.5.8 WDOG_IEN - Interrupt Enable Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 335: Prs - Peripheral Reflex System
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13. PRS - Peripheral Reflex System Quick Facts What? 0 1 2 3 The PRS (Peripheral Reflex System) allows configu- rable, fast, and autonomous communication be- tween peripherals. Why? Events and signals from one peripheral can be used as input signals or triggers by other peripherals. -
Page 336: Functional Description
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.3 Functional Description An overview of the PRS module is shown in Figure 13.1 PRS Overview on page 335. The PRS contains 12 Reflex channels. All chan- nels can select any Reflex signal offered by the producers. The consumers can choose which PRS channel to listen to and perform actions based on the Reflex signals routed through that channel. -
Page 337: Edge Detection And Clock Domains
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.3.1.2 Edge Detection and Clock Domains Using EDSEL in PRS_CHx_CTRL, edge detection can be applied to a PRS signal. When edge detection is enabled, changes in the PRS input will result in a pulse on the PRS channel. This requires that the ASYNC bit in PRS_CHx_CTRL is cleared. Signals on the PRS input must be at least one HFBUSCLK period wide in order to be detected properly. -
Page 338: Consumers
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.3.3 Consumers Consumer peripherals (Listed in Table 13.1 Reflex Consumers on page 337) can be set to listen to a PRS channel and perform an action based on the signal received on that channel. While most consumers expect a pulse input, some can handle level inputs as well. -
Page 339: Dma Request On Prs
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.3.5 DMA Request on PRS Up to two independent DMA requests can be generated by the PRS. The PRS signals triggering the DMA requests are selected with the DMAREQxSEL fields in DMA_CTRL. The DMA requests are cleared on write to the DMAREQxSEL fields and when the DMA serv- ices the requests. -
Page 340: Register Map
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_SWPULSE Software Pulse Register 0x004 PRS_SWLEVEL Software Level Register 0x008 PRS_ROUTEPEN I/O Routing Pin Enable Register... -
Page 341: Register Description
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5 Register Description 13.5.1 PRS_SWPULSE - Software Pulse Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 342: Prs_Swlevel - Software Level Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 343: Prs_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 344: Prs_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.4 PRS_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x010 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 343... - Page 345 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CH3LOC 0x00 I/O Location Decides the location of the channel I/O pin...
- Page 346 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description Value Mode Description LOC0 Location 0 LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6 Location 6 LOC7 Location 7 Reserved To ensure compatibility with future devices, always write bits to 0.
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Page 347: Prs_Routeloc1 - I/O Routing Location Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.5 PRS_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x014 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 346... - Page 348 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CH7LOC 0x00 I/O Location Decides the location of the channel I/O pin...
- Page 349 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC16 Location 16 LOC17 Location 17 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 CH5LOC 0x00...
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Page 350: Prs_Routeloc2 - I/O Routing Location Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.6 PRS_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x018 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 349... - Page 351 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CH11LOC 0x00 I/O Location Decides the location of the channel I/O pin...
- Page 352 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC10 Location 10 LOC11 Location 11 LOC12 Location 12 LOC13 Location 13 LOC14 Location 14 LOC15 Location 15 LOC16 Location 16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 353: Prs_Ctrl - Control Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.7 PRS_CTRL - Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 354: Prs_Dmareq0 - Dma Request 0 Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.8 PRS_DMAREQ0 - DMA Request 0 Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 355: Prs_Dmareq1 - Dma Request 1 Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.9 PRS_DMAREQ1 - DMA Request 1 Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 356: Prs_Peek - Prs Channel Values
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.10 PRS_PEEK - PRS Channel Values Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 357: Prs_Chx_Ctrl - Channel Control Register
EFM32JG1 Reference Manual PRS - Peripheral Reflex System 13.5.11 PRS_CHx_CTRL - Channel Control Register Offset Bit Position 0x040 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 356... - Page 358 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ASYNC Asynchronous reflex Set to enable asynchronous mode of this reflex signal Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 359 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b0011100 TIMER0 Timer 0 0b0011101 TIMER1 Timer 1 0b0101001 RTCC Real-Time Counter and Calendar 0b0110000 GPIOL General purpose Input/Output 0b0110001 GPIOH General purpose Input/Output 0b0110100 LETIMER0 Low Energy Timer 0...
- Page 360 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description SOURCESEL 0b0001000 (ADC0) 0b000 ADC0SINGLE ADC single conversion done ADC0SINGLE 0b001 ADC0SCAN ADC scan conversion done ADC0SCAN SOURCESEL = 0b0010000 (USART0) 0b000 USART0IRTX USART 0 IRDA out USART0IRTX...
- Page 361 EFM32JG1 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description SOURCESEL 0b0110000 (GPIO) 0b000 GPIOPIN0 GPIO pin 0 GPIOPIN0 (Asynchronous) 0b001 GPIOPIN1 GPIO pin 1 GPIOPIN1 (Asynchronous) 0b010 GPIOPIN2 GPIO pin 2 GPIOPIN2 (Asynchronous) 0b011 GPIOPIN3 GPIO pin 3 GPIOPIN3 (Asynchronous)
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Page 362: Pcnt - Pulse Counter
EFM32JG1 Reference Manual PCNT - Pulse Counter 14. PCNT - Pulse Counter Quick Facts What? 0 1 2 3 The Pulse Counter (PCNT) decodes incoming pul- ses. The module has a quadrature mode which may be used to decode the speed and direction of a me- chanical shaft. -
Page 363: Functional Description
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3 Functional Description An overview of the PCNT module is shown in Figure 14.1 PCNT Overview on page 362. CMU (conceptual) LFACLK Clock Triggered compare PCNTnCLK switch and clear control TCCMODE != DISABLED... -
Page 364: Quadrature Decoder Modes
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.1.3 Quadrature decoder modes Two different types of quadrature decoding is supported in the pulse counter: the externally clocked (Asynchronous) quadrature decod- ing and the oversampling (Synchronous) quadrature decoding. The externally clocked mode supports 1X quadrature decoding whereas the oversampling mode supports 1X, 2X and 4X quadrature decoding. -
Page 365: Externally Clocked Quadrature Decoder Mode
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.1.4 Externally Clocked Quadrature Decoder Mode This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field. The external pin clock source is configured by setting PCNT0CLKSEL in the CMU_PCNTCTRL register (10. - Page 366 EFM32JG1 Reference Manual PCNT - Pulse Counter Table 14.1. PCNT QUAD Mode Counter Control Function Inputs Control/Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit Note: PCNTn_S1IN is sampled on both edges of PCNTn_S0IN. silabs.com | Smart. Connected. Energy-friendly.
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Page 367: Oversampling Quadrature Decoder Mode
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.1.5 Oversampling Quadrature Decoder Mode There are three Oversampling Quadrature Decoder Modes supported: 1X , 2X and 4X. These modes are enabled by writing OVS- QUAD1X, OVSQUAD2X and OVSQUAD4X, respectively, to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field. - Page 368 EFM32JG1 Reference Manual PCNT - Pulse Counter Relationship between inputs and its state STATE S1IN S0IN ‘b00 ‘b00 ‘b00 ‘b10 ‘b10 ‘b10 ‘b01 ‘b01 ‘b01 ‘b11 ‘b11 ‘b11 OVSQUAD2X mode OVSQUAD4X mode OVSQUAD1X mode Transitions between States All state transitions updates the...
- Page 369 EFM32JG1 Reference Manual PCNT - Pulse Counter Period > 125 us S0IN S1IN Figure 14.5. PCNT Oversampling Quadrature Decoder 2X mode Period > 125 us S0IN S1IN Figure 14.6. PCNT Oversampling Quadrature Decoder 4X mode The above modes, by default are prone to flutter effects in the inputs PCNTn_S0IN and PCNTn_S1IN. When this occurs, the counter changes directions rapidly causing DIRCNG interrupts and unnecessarily waking the core.
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Page 370: Hysteresis
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.2 Hysteresis By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0. On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a monotonic value or a value that does not change directions frequently. -
Page 371: Auxiliary Counter
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.3 Auxiliary counter To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the auxiliary counter can be used. The pulse counter can, for instance, be configured to keep track of the absolute rotation of the wheel, while at the same time the auxiliary counter can keep track of how much the wheel has reversed. -
Page 372: Triggered Compare And Clear
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.4 Triggered compare and clear The pulse counter features triggered compare and clear. When enabled, a configurable trigger will induce a comparison between the main counter, PCNTn_CNT, and the top value, PCNTn_TOP. After the comparison, the counter is cleared. The trigger for a compare and clear event is configured in the TCCMODE bit-field in PCNTn_CTRL. -
Page 373: Register Access
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.5 Register Access The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3 clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is controlled from the registers in the CMU (10. -
Page 374: Edge Polarity
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.8 Edge Polarity The edge polarity can be set by configuring the EDGE bit in the PCNTn_CTRL register. When this bit is cleared, the pulse counter counts positive edges of PCNTn_S0IN input. When this bit is set, the pulse counter counts negative edges in OVSSINGLE mode. Also, when the EDGE bit is set in the OVSSINGLE and EXTCLKSINGLE modes, the PCNTn_S1IN input is inverted. -
Page 375: Direction Change Interrupt
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.10.2 Direction Change Interrupt The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) for EXTCLKQUAD and OVSQUAD1X-4X modes when the direction of the quadrature code changes. The behavior of this interrupt in the EXTCLKQUAD mode is illustrated by Figure 14.13 PCNT Direction Change Interrupt (DIRCNG) Generation on page... -
Page 376: Cascading Pulse Counters
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.3.11 Cascading Pulse Counters When two or more Pulse Counters are available, it is possible to cascade them. For example two 16-bit Pulse Counters can be casca- ded to form a 32-bit pulse counter. This can be done with the help of the CNT UF/OF PRS and CNT DIR PRS ouputs. The figure Figure 14.14 PCNT Cascading to two 16-bit PCNT to form a 32-bit PCNT on page 375... -
Page 377: Register Map
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register... -
Page 378: Register Description
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5 Register Description 14.5.1 PCNTn_CTRL - Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. - Page 379 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description TOPBHFSEL TOPB High frequency value select Apply High frequency value of TOPB to TOP register. Should be used only when RSTEN in PCNTn_CTRL is set Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 380 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description Value Mode Description DIV1 Compare and clear event each LFA cycle. DIV2 Compare and clear performed on every other LFA cycle. DIV4 Compare and clear performed on every 4th LFA cycle.
- Page 381 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description Selects whether the regular counter responds to up-count events, down-count events or both Value Mode Description BOTH Counts up on up-count and down on down-count events. Only counts up on up-count events.
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Page 382: Pcntn_Cmd - Command Register (Async Reg)
EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description OVSQUAD1X LFACLK oversampling quadrature decoder 1X mode (available in EM0- EM3). OVSQUAD2X LFACLK oversampling quadrature decoder 2X mode (available in EM0- EM3). OVSQUAD4X LFACLK oversampling quadrature decoder 4X mode (available in EM0- EM3). -
Page 383: Pcntn_Cnt - Counter Value Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.4 PCNTn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 384: Pcntn_Topb - Top Value Buffer Register (Async Reg)
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset... -
Page 385: Pcntn_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.8 PCNTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 386: Pcntn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.9 PCNTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 387: Pcntn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.10 PCNTn_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 388: Pcntn_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x02C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 387... - Page 389 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 S1INLOC 0x00 I/O Location Defines the location of the PCNT S1IN input pin.
- Page 390 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S0INLOC 0x00 I/O Location Defines the location of the PCNT S0IN input pin.
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Page 391: Pcntn_Freeze - Freeze Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.12 PCNTn_FREEZE - Freeze Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 392: Pcntn_Auxcnt - Auxiliary Counter Value Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 393: Pcntn_Input - Pcnt Input Register
EFM32JG1 Reference Manual PCNT - Pulse Counter 14.5.15 PCNTn_INPUT - PCNT Input Register Offset Bit Position 0x068 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 392... - Page 394 EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S1PRSEN S1IN PRS Enable When set, the PRS channel is selected as input to S1IN.
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Page 395: Pcntn_Ovscfg - Oversampling Config Register (Async Reg)
EFM32JG1 Reference Manual PCNT - Pulse Counter Name Reset Access Description PRSCH10 PRS Channel 10 selected. PRSCH11 PRS Channel 11 selected. 14.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). -
Page 396: I2C - Inter-Integrated Circuit Interface
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15. I2C - Inter-Integrated Circuit Interface Quick Facts What? 0 1 2 3 The I C interface allows communication on I buses with the lowest energy consumption possible. Why? C is a popular serial bus that enables communica-... -
Page 397: Functional Description
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3 Functional Description An overview of the I2C module is shown in Figure 15.1 I2C Overview on page 396. Peripheral Bus C Control and Transmit Buffer Receive Buffer Status (2-level FIFO) (2-level FIFO) -
Page 398: I2C-Bus Overview
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.1 I2C-Bus Overview The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 15.2 I2C-Bus Example on page 397. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss. -
Page 399: Start And Stop Conditions
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus. All transactions on the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 15.4 I2C START and STOP Conditions on page... -
Page 400: Bus Transfer
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.1.2 Bus Transfer When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave (R/W bit set to 0). -
Page 401: Addresses
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.1.3 Addresses C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses are summarized in Table 15.1 I2C Reserved I... -
Page 402: Arbitration, Clock Synchronization, Clock Stretching
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.1.5 Arbitration, Clock Synchronization, Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration. -
Page 403: Arbitration
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value. -
Page 404: Receive Buffer And Shift Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.6.2 Receive Buffer and Shift Register The I C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 15.14 I2C Receive Buffer Operation on page 403. -
Page 405: Master Operation
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.7 Master Operation A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I C module generate a start condition whenever the bus becomes free. -
Page 406: Master State Machine
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.7.1 Master State Machine The master state machine is shown in Figure 15.15 I2C Master State Machine on page 405. A master operation starts in the far left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine. -
Page 407: Interactions
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module. -
Page 408: Automatic Ack Interaction
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e., the interaction closest to the top of Table 15.2 I2C Interactions in Prioritized Order on page 406 is applied to the bus. -
Page 409: Master Transmitter
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.7.5 Master Transmitter To transmit data to a slave, the master must operate as a master transmitter. Table 15.3 I2C Master Transmitter on page 408 shows the states the I C module goes through while acting as a master transmitter. Every state where an interaction is required has the possi- ble interactions listed, along with the result of the interactions. - Page 410 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0x97 ADDR+W transmitted, ACK interrupt flag TXDATA DATA will be sent ACK received (BUSHOLD interrupt STOP STOP will be sent. Bus will be released flag)
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Page 411: Master Receiver
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.7.6 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 15.4 I2C Master Receiver on page 410. This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The ad- dress byte loaded into the data register thus has to contain the 7-bit slave address in the 7 most significant bits of the byte, and have the least significant bit set. - Page 412 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0xB3 Data received RXDATA interrupt ACK + RXDA- ACK will be transmitted, reception continues flag(BUSHOLD inter- rupt flag) NACK + NACK will be transmitted, reception continues...
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Page 413: Bus States
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I... -
Page 414: Slave State Machine
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.9.1 Slave State Machine The slave state machine is shown in Figure 15.16 I2C Slave State Machine on page 413. The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission pro- ceed. -
Page 415: Slave Transmitter
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave until room is available in the shift register. - Page 416 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0xDD Data transmitted, NACK NACK interrupt flag None The slave goes idle received (BUSHOLD interrupt CONT + DATA will be transmitted flag) TXDATA Stop received...
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Page 417: Slave Receiver
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.9.4 Slave Receiver A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiv- er mode. -
Page 418: Dma
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.10.1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft- ware is thus relieved of moving data to and from memory after each transferred byte. -
Page 419: I2C-Bus Errors
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.12.3 I2C-Bus Errors An I C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is high during bit-transmission on the I C-bus. -
Page 420: Clock Low Error
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.3.12.7 Clock Low Error The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications are identical. A case may arise when (before an arbitration has been decided upon) the I C module decides to send out a repeated START or a STOP condition while the other device is still sending data. -
Page 421: Register Map
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS... -
Page 422: Register Description
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5 Register Description 15.5.1 I2Cn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 421... - Page 423 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 18:16 CLTO Clock Low Timeout Use to generate a timeout when CLK has been low for the given amount of time. Wraps around and continues counting when the timeout is reached.
- Page 424 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 425 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description The master automatically sends a STOP if a NACK is received from a slave. AUTOSE Automatic STOP when Empty Write to 1 to make a master transmitter send a STOP when no more data is available for transmission.
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Page 426: I2Cn_Cmd - Command Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.2 I2Cn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 427: I2Cn_State - State Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 428: I2Cn_Status - Status Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.4 I2Cn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 429: I2Cn_Clkdiv - Clock Division Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.5 I2Cn_CLKDIV - Clock Division Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 430: I2Cn_Saddrmask - Slave Address Mask Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.7 I2Cn_SADDRMASK - Slave Address Mask Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 431: I2Cn_Rxdouble - Receive Buffer Double Data Register (Actionable Reads)
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 432: I2Cn_Rxdoublep - Receive Buffer Double Data Peek Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 433: I2Cn_Txdouble - Transmit Buffer Double Data Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 434: I2Cn_If - Interrupt Flag Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.14 I2Cn_IF - Interrupt Flag Register Offset Bit Position 0x034 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 433... - Page 435 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR Clock Low Error Interrupt Flag Set when the clock is pulled low before a START or a STOP condition could be transmitted.
- Page 436 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set when a repeated start condition is detected. START START condition Interrupt Flag Set when a start condition is successfully transmitted. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 435...
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Page 437: I2Cn_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.15 I2Cn_IFS - Interrupt Flag Set Register Offset Bit Position 0x038 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 436... - Page 438 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR Set CLERR Interrupt Flag Write 1 to set the CLERR interrupt flag...
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Page 439: I2Cn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.16 I2Cn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x03C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 438... - Page 440 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR (R)W1 Clear CLERR Interrupt Flag Write 1 to clear the CLERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 441 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Write 1 to clear the TXC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 442: I2Cn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.17 I2Cn_IEN - Interrupt Enable Register Offset Bit Position 0x040 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 441... - Page 443 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR CLERR Interrupt Enable Enable/disable the CLERR interrupt RXFULL...
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Page 444: I2Cn_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description START START Interrupt Enable Enable/disable the START interrupt 15.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. -
Page 445: I2Cn_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface 15.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x048 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 444... - Page 446 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 SCLLOC 0x00 I/O Location Decides the location of the I C SCL pin.
- Page 447 EFM32JG1 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SDALOC 0x00 I/O Location Decides the location of the I C SDA pin.
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Page 448: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16. USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? 0 1 2 3 The USART handles high-speed UART, SPI-bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the USART allows efficient com- munication with a wide range of external devices. -
Page 449: Features
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.2 Features • Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit multiple entry buffers, with additional separate shift registers •... -
Page 450: Functional Description
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3 Functional Description An overview of the USART module is shown in Figure 16.1 USART Overview on page 449. USn_CTS Peripheral Bus USn_RTS USn_CS UART Control TX Buffer RX Buffer and status... -
Page 451: Modes Of Operation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.1 Modes of Operation The USART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both the master and slave sample and transmit data according to this clock. -
Page 452: Frame Format
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization. -
Page 453: Parity Bit Calculation And Handling
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first. -
Page 454: Clock Generation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.3 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Figure 16.3 USART Baud Rate on page 453. -
Page 455: Auto Baud Detection
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USARTn_OVS =00 USARTn_OVS =01 Desired baud USARTn_CLKDIV/256 Actual baud rate USARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error % (to 32nd position) [baud/s] (to 32nd position) [baud/s] 57600 3,34375 57553,96... -
Page 456: Transmit Buffer Operation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.6 Transmit Buffer Operation The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buf- fer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer. -
Page 457: Frame Transmission Control
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.7 Frame Transmission Control The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g. -
Page 458: Receive Buffer Operation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.9 Receive Buffer Operation When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set. -
Page 459: Blocking Incoming Data
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.10 Blocking Incoming Data When using hardware frame recognition, as detailed in 16.3.2.20 Multi-Processor Mode 16.3.2.21 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. -
Page 460: Clock Recovery And Filtering
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.11 Clock Recovery and Filtering The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors. -
Page 461: Parity Error
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 16.8. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices. -
Page 462: Local Loopback
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.14 Local Loopback The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev- er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 16.9 USART Local... -
Page 463: Single Data-Link With External Driver
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.17 Single Data-link with External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. -
Page 464: Large Frames
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.19 Large Frames As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits. - Page 465 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Figure 16.12 USART Transmission of Large Frames, MSBF on page 463 illustrates the order of the transmitted bits when an 11 bit frame is transmitted with MSBF set. If MSBF is set and the frame is smaller than 10 bits, only the contents of transmit buffer 0 will be transmitted.
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Page 466: Multi-Processor Mode
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.20 Multi-Processor Mode To simplify communication between multiple processors, the USART supports a special multi-processor mode. In this mode the 9th da- ta bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address. -
Page 467: Smartcard Mode
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.2.22 SmartCard Mode In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error. -
Page 468: Synchronous Operation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 1/2 stop bit NAK or stop Stop 13 14 15 16 1 9 10 11 14 15 16 17 18 X Figure 16.17. USART SmartCard Stop Bit Sampling For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers. -
Page 469: Clock Generation
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 16.18 USART Synchronous Mode Bit Rate on page 468. As in the case of asyn- chronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part. -
Page 470: Master Mode
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available. If CPHA=0, TXUF is set if data is not available in the transmit buffer three HFPERCLK cycles prior to the first sample clock edge. The RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first sample clock edge if the receive buffer overflows. -
Page 471: Slave Mode
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.3.6 Slave Mode When the USART is in slave mode, data transmission is not controlled by the USART, but by an external master. The USART is there- fore not able to initiate a transmission, and has no control over the number of bytes written to the master. -
Page 472: Major Modes
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.3.10 Major Modes The USART supports a set of different I2S formats as shown in Table 16.9 USART I2S Modes on page 471, but it is not limited to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO ena- bles mono mode, i.e. - Page 473 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USn_CLK USn_CS (word select) USn_TX/ USn_RX Right channel Left channel Right channel Figure 16.23. USART Left-justified I2S waveform A right-justified stream is shown in Figure 16.24 USART Right-justified I2S waveform on page 472.
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Page 474: Using I2S Mode
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.3.11 Using I2S Mode When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared. -
Page 475: Prs Clk Input
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.8 PRS CLK Input The USART can be configured to receive clock directly from a PRS channel by setting CLKPRS in USARTn_INPUT. The PRS channel used is selected using CLKPRSSEL in USARTn_INPUT. This is useful in synchronous slave mode and can together with RX PRS input be used to input data from PRS. -
Page 476: Timer
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.10 Timer In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter. - Page 477 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter TIMECMP2 TIMECMP1 TIMECMP0 TCMPn TXST RXACT TCMPVALn RXACTN TSTOP GP_CNT[7:0] clear DISABLE TCMP TXEOF Compare TCMPn enable RXACT RXEOF TSTART START_An RESTARTEN START_Bn START_A2 START_B2 START_A1 start START_B1 event START_A0 8 bit...
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Page 478: Response Timeout
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Application TSTARTn TSTOPn TCMPVALn Other Break Detect TSTART1 = RXACT TSTOP1 = TCMPVAL1 TCMP1 in USARTn_IEN RXACTN = 0x0C TX delayed start of transmission and TSTART0 = DISA- TSTOP0 = TCMP0,... -
Page 479: Rx Timeout
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.10.2 RX Timeout A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT to disable the comparator. See Table 16.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 476... -
Page 480: Tx Start Delay
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.10.4 TX Start Delay Some applications may require a delay before the start of transmission. This example in Figure 16.30 USART TXSEQ Timing on page shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with CS asserted. -
Page 481: Combined Tx And Rx Example
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.10.8 Combined TX and RX Example This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The TSTOP1 is set to TCMP1 to generate an event after 28 baud times. -
Page 482: Irda Modulator/ Demodulator
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.3.12 IrDA Modulator/ Demodulator The IrDA modulator on USART0 implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The modulator takes the signal output from the USART module, and modulates it before it leaves USART0. In the same way, the input signal is demodulated before it enters the actual USART module. -
Page 483: Register Map
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control register... -
Page 484: Register Description
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5 Register Description 16.5.1 USARTn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 483... - Page 485 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description SMSDELAY Synchronous Master Sample Delay Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds MVDIS Majority Vote Disable Disable majority vote for 16x, 8x and 6x oversampling modes.
- Page 486 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set. SCRETRANS SmartCard Retransmit When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still ena- bled.
- Page 487 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. CSMA Action On Slave-Select In Master Mode This register determines the action to be performed when slave-select is configured as an input and driven low while in master mode.
- Page 488 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.
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Page 489: Usartn_Frame - Usart Frame Format Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.2 USARTn_FRAME - USART Frame Format Register Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 488... - Page 490 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:12 STOPBITS Stop-Bit Mode Determines the number of stop-bits used.
- Page 491 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description SIXTEEN Each frame contains 16 data bits silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 490...
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Page 492: Usartn_Trigctrl - Usart Trigger Control Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.3 USARTn_TRIGCTRL - USART Trigger Control register Offset Bit Position 0x008 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 491... - Page 493 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16 TSEL Trigger PRS Channel Select Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN.
- Page 494 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXTEN Receive Trigger Enable When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
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Page 495: Usartn_Cmd - Command Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.4 USARTn_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 496: Usartn_Status - Usart Status Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 495... - Page 497 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16 TXBUFCNT TX Buffer Count Count of TX buffer entry 0, entry 1, and TX shift register. For large frames, the count is only of TX buffer entry 0 and the TX shifter register.
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Page 498: Usartn_Clkdiv - Clock Control Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set when the transmitter is enabled. RXENS Receiver Enable Status Set when the receiver is enabled. 16.5.6 USARTn_CLKDIV - Clock Control Register Offset Bit Position 0x014 Reset... -
Page 499: Usartn_Rxdatax - Rx Buffer Data Extended Register (Actionable Reads)
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 500: Usartn_Rxdoublex - Rx Buffer Double Data Extended Register (Actionable Reads)
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. -
Page 501: Usartn_Rxdouble - Rx Fifo Double Data Register (Actionable Reads)
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 502: Usartn_Rxdoublexp - Rx Buffer Double Data Extended Peek Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. -
Page 503: Usartn_Txdatax - Tx Buffer Data Extended Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 504: Usartn_Txdata - Tx Buffer Data Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.14 USARTn_TXDATA - TX Buffer Data Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 505: Usartn_Txdoublex - Tx Buffer Double Data Extended Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description RXENAT1 Enable RX After Transmission Set to enable reception after transmission. -
Page 506: Usartn_Txdouble - Tx Buffer Double Data Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 507: Usartn_If - Interrupt Flag Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.17 USARTn_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 506... - Page 508 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2 Timer comparator 2 Interrupt Flag Set when the timer reaches the comparator 2 value, TCMP2.
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Page 509: Usartn_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.18 USARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 508... - Page 510 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2 Set TCMP2 Interrupt Flag Write 1 to set the TCMP2 interrupt flag...
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Page 511: Usartn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.19 USARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 510... - Page 512 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2 (R)W1 Clear TCMP2 Interrupt Flag Write 1 to clear the TCMP2 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
- Page 513 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions (R)W1 Clear TXC Interrupt Flag Write 1 to clear the TXC interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 514: Usartn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.20 USARTn_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 513... - Page 515 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2 TCMP2 Interrupt Enable Enable/disable the TCMP2 interrupt...
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Page 516: Usartn_Irctrl - Irda Control Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.21 USARTn_IRCTRL - IrDA Control Register Offset Bit Position 0x050 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 515... - Page 517 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:8 IRPRSSEL IrDA PRS Channel Select A PRS can be used as input to the pulse modulator instead of TX. This value selects the channel to use.
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Page 518: Usartn_Input - Usart Input Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.22 USARTn_INPUT - USART Input Register Offset Bit Position 0x058 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 517... - Page 519 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKPRS PRS CLK Enable When set, the PRS channel selected as input to CLK.
- Page 520 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description PRSCH10 PRS Channel 10 selected PRSCH11 PRS Channel 11 selected silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 519...
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Page 521: Usartn_I2Sctrl - I2S Control Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.23 USARTn_I2SCTRL - I2S Control Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 522: Usartn_Timing - Timing Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.24 USARTn_TIMING - Timing Register Offset Bit Position 0x060 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 521... - Page 523 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSHOLD Chip Select Hold Chip Select will be asserted after the end of frame transmission. When using TCMPn, normally set TIMECMPn_TSTART to DISABLE to stop general timer and to prevent unwanted interrupts.
- Page 524 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description THREE CS is asserted for 3 baud-times before start of transmission SEVEN CS is asserted for 7 baud-times before start of transmission TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-...
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Page 525: Usartn_Ctrlx - Control Register Extended
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.25 USARTn_CTRLX - Control Register Extended Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 526: Usartn_Timecmp0 - Used To Generate Interrupts And Various Delays
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.26 USARTn_TIMECMP0 - Used to generate interrupts and various delays Offset Bit Position 0x068 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 525... - Page 527 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN Restart Timer on TCMP0 Each TCMP0 event will reset and restart the timer...
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Page 528: Usartn_Timecmp1 - Used To Generate Interrupts And Various Delays
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.27 USARTn_TIMECMP1 - Used to generate interrupts and various delays Offset Bit Position 0x06C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 527... - Page 529 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN Restart Timer on TCMP1 Each TCMP1 event will reset and restart the timer...
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Page 530: Usartn_Timecmp2 - Used To Generate Interrupts And Various Delays
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.28 USARTn_TIMECMP2 - Used to generate interrupts and various delays Offset Bit Position 0x070 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 529... - Page 531 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN Restart Timer on TCMP2 Each TCMP2 event will reset and restart the timer...
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Page 532: Usartn_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x074 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 531... - Page 533 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTSPEN RTS Pin Enable When set, the RTS pin of the USART is enabled.
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Page 534: Usartn_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x078 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 533... - Page 535 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CLKLOC 0x00 I/O Location Decides the location of the USART CLK pin.
- Page 536 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 CSLOC 0x00 I/O Location Decides the location of the USART CS pin.
- Page 537 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 TXLOC 0x00 I/O Location Decides the location of the USART TX pin.
- Page 538 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC 0x00 I/O Location Decides the location of the USART RX pin.
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Page 539: Usartn_Routeloc1 - I/O Routing Location Register
EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 16.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x07C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 538... - Page 540 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 RTSLOC 0x00 I/O Location Decides the location of the USART RTS pin.
- Page 541 EFM32JG1 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CTSLOC 0x00 I/O Location Decides the location of the USART CTS pin.
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Page 542: Leuart - Low Energy Universal Asynchronous Receiver/Transmitter
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? 0 1 2 3 The LEUART provides full UART communication us- ing a low frequency 32.768 kHz clock, and has spe- cial features for communication without CPU inter- vention. -
Page 543: Features
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.2 Features • Low energy asynchronous serial communications • Full/half duplex communication • Separate TX / RX enable • Separate double buffered transmit buffer and receive buffer • Programmable baud rate, generated as a fractional division of the LFBCLK •... -
Page 544: Functional Description
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3 Functional Description An overview of the LEUART module is shown in Figure 17.1 LEUART Overview on page 543. Peripheral Bus UART Control TX Buffer RX Buffer and status !RXBLOCK... -
Page 545: Frame Format
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.1 Frame Format The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization. -
Page 546: Clock Generation
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.3 Clock Generation The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART. -
Page 547: Transmit Buffer Operation
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.4.1 Transmit Buffer Operation A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX. Using LEUARTn_TXDATA allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in LEUARTn_CTRL. -
Page 548: Data Reception
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.5 Data Reception Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start bit of a new frame. When a start bit is found, reception of the new frame begins if the receive shift register is empty and ready for new data. -
Page 549: Blocking Incoming Data
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.5.2 Blocking Incoming Data When using hardware frame recognition, as detailed in 17.3.5.6 Programmable Start Frame, 17.3.5.7 Programmable Signal Frame, and 17.3.5.8 Multi-Processor Mode, it is necessary to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. -
Page 550: Framing Error And Break Detection
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.5.5 Framing Error and Break Detection A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose. -
Page 551: Multi-Processor Mode
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.5.8 Multi-Processor Mode To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-pro- cessor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address. -
Page 552: Single Data-Link
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.7.1 Single Data-link In this setup, the LEUART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in LEUARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the LEUART transmitter does not drive the line when receiving data, as this would corrupt the data on the line. -
Page 553: Prs Rx Input
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.9 PRS RX Input In addition to receiving data on an external pin the LEUART can be configured to receive data directly from a PRS channel by setting RX_PRS in LEUARTn_INPUT. The PRS channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT. See the PRS chapter for more details on the PRS block. -
Page 554: Pulse Generator/ Pulse Extender
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.3.11 Pulse Generator/ Pulse Extender The LEUART has an optional pulse generator for the transmitter output, and a pulse extender on the receiver input. These are enabled by setting PULSEEN in LEUARTn_PULSECTRL, and with INV in LEUARTn_CTRL set, they will change the output/input format of the LEUART from NRZ to RZI as shown in Figure 17.11 LEUART - NRZ vs. -
Page 555: Register Map
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LEUARTn_CTRL Control Register 0x004 LEUARTn_CMD Command Register 0x008 LEUARTn_STATUS Status Register... -
Page 556: Register Description
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5 Register Description 17.5.1 LEUARTn_CTRL - Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset... - Page 557 EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:14 TXDELAY TX Delay Transmission Configurable delay before new transfers. Frames sent back-to-back are not delayed.
- Page 558 EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description Value Description Detected start-frames have no effect on RXBLOCK When a start-frame is detected, RXBLOCK is cleared and the start- frame is loaded into the receive buffer...
- Page 559 EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description Value Mode Description EIGHT Each frame contains 8 data bits NINE Each frame contains 9 data bits AUTOTRI Automatic Transmitter Tristate When set, LEUn_TX is tristated whenever the transmitter is inactive.
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Page 560: Leuartn_Cmd - Command Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.2 LEUARTn_CMD - Command Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name... -
Page 561: Leuartn_Status - Status Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.3 LEUARTn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 562: Leuartn_Clkdiv - Clock Control Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name... -
Page 563: Leuartn_Sigframe - Signal Frame Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name... -
Page 564: Leuartn_Rxdata - Receive Buffer Data Register (Actionable Reads)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 565: Leuartn_Txdatax - Transmit Buffer Data Extended Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x024 Reset... -
Page 566: Leuartn_Txdata - Transmit Buffer Data Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x028 Reset Access... -
Page 567: Leuartn_If - Interrupt Flag Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.12 LEUARTn_IF - Interrupt Flag Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 568: Leuartn_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.13 LEUARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 569: Leuartn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.14 LEUARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 570: Leuartn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.15 LEUARTn_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 571: Leuartn_Pulsectrl - Pulse Control Register (Async Reg)
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x03C Reset Access Name... -
Page 572: Leuartn_Freeze - Freeze Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.17 LEUARTn_FREEZE - Freeze Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 573: Leuartn_Syncbusy - Synchronization Busy Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 574: Leuartn_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 575: Leuartn_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x058 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 574... - Page 576 EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 TXLOC 0x00 I/O Location Decides the location of the LEUART TX pin. See the device datasheet for the mapping between location and physical pins.
- Page 577 EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC 0x00 I/O Location Decides the location of the LEUART RX pin. See the device datasheet for the mapping between location and physical pins.
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Page 578: Leuartn_Input - Leuart Input Register
EFM32JG1 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 17.5.21 LEUARTn_INPUT - LEUART Input Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 579: Timer - Timer/Counter
EFM32JG1 Reference Manual TIMER - Timer/Counter 18. TIMER - Timer/Counter Quick Facts What? 0 1 2 3 The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms and triggers timed actions in other peripherals. Why? Most applications have activities that need to be... -
Page 580: Features
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.2 Features • 16-bit auto reload up/down counter • Dedicated 16-bit reload register which serves as counter maximum • 3 or 4 Compare/Capture channels • Individually configurable as either input capture or output compare/PWM •... -
Page 581: Functional Description
EFM32JG1 Reference Manual TIMER - Timer/Counter • Set outputs inactive • Clear output • Tristate output • Individual fault sources • One or two PRS signals • Debugger • Support for automatic restart • Core lockup • Configuration lock 18.3 Functional Description An overview of the TIMER module is shown in Figure 18.1 TIMER Block Overview on page 580... -
Page 582: Events
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.1.1 Events Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In up-count mode and Quadrature Decoder mode the next value is 0. In up/down-count mode, the next value is TIMERn_TOP-1. -
Page 583: Clock Source
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.1.3 Clock Source The counter can be clocked from several sources, which are all synchronized with the peripheral clock (HFPERCLK). See Figure 18.3 TIMER Clock Selection on page 582. Counter PRESC CLKSEL (Controlled by TIMERn_CTRL) -
Page 584: Top Value Buffer
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.1.8 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the actual count value. -
Page 585: Quadrature Decoder
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.1.9 Quadrature Decoder Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses two input channels that are 90 degrees out of phase (see Figure 18.6 TIMER Quadrature Encoded Inputs on page 584). -
Page 586: X2 Decoding Mode
EFM32JG1 Reference Manual TIMER - Timer/Counter The Quadrature Decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in TIMERn_CTRL. See Figure 18.7 TIMER Quadrature Decoder Configuration on page 584 18.3.1.10 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 18.1 TIMER Counter Response in... -
Page 587: Timer Rotational Position
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.1.12 TIMER Rotational Position To calculate a position Figure 18.10 TIMER Rotational Position Equation on page 586 can be used. pos° = (CNT/X x N) x 360° Figure 18.10. TIMER Rotational Position Equation where X = Encoding type and N = Number of pulses per revolution. -
Page 588: Input Capture
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.3 Input Capture In Input Capture Mode, the counter value (TIMERn_CNT) can be captured in the Compare/Capture Register (TIMERn_CCx_CCV) (see Figure 18.12 TIMER Input Capture on page 587). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that triggered the capture in TIMERn_CCx_CCV. -
Page 589: Period/Pulse-Width Capture
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.4 Period/Pulse-Width Capture Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either exter- nal pin or PRS, see Figure 18.13 TIMER Period and/or Pulse width Capture on page... -
Page 590: Compare
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.5 Compare Each Compare/Capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_CCV matches the counter value, see Figure 18.14 TIMER Block Diagram Showing Comparison Functionality on page 589. In compare mode, each compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or underflow). -
Page 591: Compare Mode Registers
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.6 Compare Mode Registers When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Com- pare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL. -
Page 592: Frequency Generation (Frg)
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.7 Frequency Generation (FRG) Frequency generation (see Figure 18.17 TIMER Up-count Frequency Generation on page 591) can be achieved in compare mode by: • Setting the counter in up-count mode • Enabling buffering of the TOP value. -
Page 593: Up-Count (Single-Slope) Pwm
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.9 Up-count (Single-slope) PWM If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope PWM output will be generated (see Figure 18.20 TIMER Up-count PWM Generation on page 592). -
Page 594: Count Mode
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.10 2x Count Mode When the timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 18.25 TIMER CC out in 2x mode on page 593... -
Page 595: Up/Down-Count (Dual-Slope) Pwm
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.11 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated Figure 18.29 TIMER Up/Down-count PWM Generation on page 594.The resolution (in bits) is given by... -
Page 596: Count Mode
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.2.12 2x Count Mode When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 18.34 TIMER CC out in 2x mode on page 595... -
Page 597: Dead-Time Insertion Unit (Timer0 Only)
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.3 Dead-Time Insertion Unit (TIMER0 only) The Dead-Time Insertion Unit aims to make control of brushless DC (BLDC) motors safer and more efficient by introducing complemen- tary PWM outputs with dead-time insertion and fault handling, see Figure 18.39 TIMER Dead-Time Insertion Unit Overview on page... - Page 598 EFM32JG1 Reference Manual TIMER - Timer/Counter DTFALLT DTRISET Select Original PWM (TIM0_CCx_pre) HFPERCLK Clock control Counter TIMERn Primary output (TIM0_CCx) Complementary Output (TIM0_CDTIx) Figure 18.41. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
- Page 599 EFM32JG1 Reference Manual TIMER - Timer/Counter Table 18.3. DTI output when timer halted DTAR DTFATS State frozen safe running running silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 598...
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Page 600: Output Polarity
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.3.1 Output Polarity The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of the outputs can be changed however, if this is required by the application. The active values of the primary and complementary outputs are set by the DTIPOL and DTCINV bits in the TIMER0_DTCTRL register. -
Page 601: Prs Channel As A Source
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.3.2 PRS Channel as a Source A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN in TIMER0_DTCTRL will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS channel. -
Page 602: Interrupts, Dma And Prs Output
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.3.5 Interrupts, DMA and PRS Output The timer has 3 different types of output events: • Counter Underflow • Counter Overflow • Compare match or input capture (one per Compare/Capture channel) Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture channel which is set on buffer overflow in capture mode. -
Page 603: Register Map
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IF Interrupt Flag Register... -
Page 604: Register Description
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5 Register Description 18.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 603... - Page 605 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RSSCOIST Reload-Start Sets Compare Ouptut initial State When set, compare output is set to COIST value at Reload-Start event...
- Page 606 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description NONE No action START Start counter without reload STOP Stop counter without reload RELOADSTART Reload and start counter RISEA Timer Rising Input Edge Action These bits select the action taken in the counter when a rising edge occurs on the input.
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Page 607: Timern_Cmd - Command Register
EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description Value Mode Description Up-count mode DOWN Down-count mode UPDOWN Up/down-count mode QDEC Quadrature decoder mode 18.5.2 TIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access... -
Page 608: Timern_Status - Status Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.3 TIMERn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 607... - Page 609 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CCPOL3 CC3 Polarity In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC3_CCV. In Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 3.
- Page 610 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description ICV2 CC2 Input Capture Valid This bit indicates that TIMERn_CC2_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off).
- Page 611 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description This field indicates that the TIMERn_CC1_CCVB registers contain data which have not been written to TIMERn_CC1_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to 0b00 (Off).
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Page 612: Timern_If - Interrupt Flag Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.4 TIMERn_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 613: Timern_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.5 TIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 614: Timern_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.6 TIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 613... - Page 615 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 (R)W1 Clear ICBOF3 Interrupt Flag Write 1 to clear the ICBOF3 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
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Page 616: Timern_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.7 TIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 617: Timern_Top - Counter Top Value Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.8 TIMERn_TOP - Counter Top Value Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 618: Timern_Cnt - Counter Value Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.10 TIMERn_CNT - Counter Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 619: Timern_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 620: Timern_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x034 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 619... - Page 621 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CC3LOC 0x00 I/O Location Decides the location of the CC3 pin.
- Page 622 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 CC2LOC 0x00 I/O Location Decides the location of the CC2 pin.
- Page 623 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 CC1LOC 0x00 I/O Location Decides the location of the CC1 pin.
- Page 624 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CC0LOC 0x00 I/O Location Decides the location of the CC0 pin. Value...
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Page 625: Timern_Routeloc2 - I/O Routing Location Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x03C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 624... - Page 626 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 CDTI2LOC 0x00 I/O Location Decides the location of the CDTI2 pin.
- Page 627 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 CDTI1LOC 0x00 I/O Location Decides the location of the CDTI1 pin.
- Page 628 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CDTI0LOC 0x00 I/O Location Decides the location of the CDTI0 pin. Value...
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Page 629: Timern_Ccx_Ctrl - Cc Channel Control Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.15 TIMERn_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x060 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 628... - Page 630 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FILT Digital Filter Enable digital filter. Value Mode Description DISABLE Digital filter disabled...
- Page 631 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 19:16 PRSSEL Compare/Capture Channel PRS Input Channel Selection Select PRS input channel for Compare/Capture channel. Value Mode Description PRSCH0 PRS Channel 0 selected as input PRSCH1 PRS Channel 1 selected as input...
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Page 632: Timern_Ccx_Ccv - Cc Channel Value Register (Actionable Reads)
EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description CLEAR Clear output on compare match Set output on compare match Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions COIST Compare Output Initial State This bit is only used in Output Compare and PWM mode. -
Page 633: Timern_Ccx_Ccvp - Cc Channel Value Peek Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 634: Timern_Dtctrl - Dti Control Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.19 TIMERn_DTCTRL - DTI Control Register Offset Bit Position 0x0A0 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 633... - Page 635 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTPRSEN DTI PRS Source Enable Enable/disable PRS as DTI input. 23:11 Reserved To ensure compatibility with future devices, always write bits to 0.
- Page 636 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description RESTART DTI restart on debugger exit DTEN DTI Enable Enable/disable DTI. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 635...
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Page 637: Timern_Dttime - Dti Time Control Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.20 TIMERn_DTTIME - DTI Time Control Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 638: Timern_Dtfc - Dti Fault Configuration Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.21 TIMERn_DTFC - DTI Fault Configuration Register Offset Bit Position 0x0A8 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 637... - Page 639 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTLOCKUPFEN DTI Lockup Fault Enable Set this bit to 1 to enable core lockup as a fault source...
- Page 640 EFM32JG1 Reference Manual TIMER - Timer/Counter Name Reset Access Description DTPRS0FSEL DTI PRS Fault Source 0 Select Select PRS channel for fault source 0. Value Mode Description PRSCH0 PRS Channel 0 selected as fault source 0 PRSCH1 PRS Channel 1 selected as fault source 1...
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Page 641: Timern_Dtogen - Dti Output Generation Enable Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 642: Timern_Dtfault - Dti Fault Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.23 TIMERn_DTFAULT - DTI Fault Register Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 643: Timern_Dtfaultc - Dti Fault Clear Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 644: Timern_Dtlock - Dti Configuration Lock Register
EFM32JG1 Reference Manual TIMER - Timer/Counter 18.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 645: Letimer - Low Energy Timer
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19. LETIMER - Low Energy Timer Quick Facts What? 0 1 2 3 The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32.768 Hz, clock the LETIMER is available in EM2 DeepSleep. -
Page 646: Functional Description
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3 Functional Description An overview of the LETIMER module is shown in Figure 19.1 LETIMER Overview on page 645. The LETIMER is a 16-bit down-coun- ter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter. -
Page 647: Top Value
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3 Top Value If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0 is loaded into LETIMERn_CNT on timer underflow. If COMP0TOP is cleared to 0, the timer wraps around to 0xFFFF. The underflow interrupt flag UF in LETIMERn_IF is set when the timer reaches zero. -
Page 648: Free-Running Mode
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3.3 Free-Running Mode In free-running mode, the LETIMER acts as a regular timer and the repeat counter is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in Figure 19.2 LETIMER State... -
Page 649: One-Shot Mode
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3.4 One-shot Mode The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI- MERn_REP0 times, i.e. -
Page 650: Buffered Mode
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3.5 Buffered Mode The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI- MERn_REP1 has been written since the last time it was used and it is nonzero, LETIMERn_REP1 is then loaded into LETI- MERn_REP0, and counting continues the new number of times. -
Page 651: Double Mode
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3.6 Double Mode The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0. -
Page 652: Prs Input Triggers
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.3.8 PRS Input Triggers The LETIMER can be configured to start, stop, and/or clear based on PRS inputs. The diagram showing the functions of the PRS input triggers is shown in Figure 19.7 LETIMER PRS input triggers. on page 651. -
Page 653: Underflow Output Action
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.4 Underflow Output Action For each of the repeat registers, an underflow output action can be set. The configured output action is performed every time the coun- ter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero. - Page 654 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Initial configuration COMP0 Int. flags set UFIF UFIF UFIF UFIF UFIF UFIF LFACLK LETIMERn LETn_O0 UFOA0 = 00 LETn_O0 UFOA0 = 01 LETn_O0 UFOA0 = 10 Figure 19.8. LETIMER Simple Waveforms Output For the example in Figure 19.9 LETIMER Repeated Counting on page...
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Page 655: Prs Output
EFM32JG1 Reference Manual LETIMER - Low Energy Timer UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 Figure 19.10. LETIMER Dual Output 19.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system. -
Page 656: Triggered Output Generation
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.6.1 Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started. -
Page 657: Continuous Output Generation
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.6.2 Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 19.8 LETIMER Simple Waveforms Output on page... -
Page 658: Pwm Output
EFM32JG1 Reference Manual LETIMER - Low Energy Timer The final result is shown in Figure 19.12 LETIMER Continuous Operation on page 656. The pulse output is grouped to show which sequence generated which output. Toggle output is also shown in the figure. Note that the toggle output is not aligned with the pulse outputs. -
Page 659: Register Access
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.3.7 Register access This module is a Low Energy Peripheral, and supports immediate synchronization. For description regarding immediate synchroniza- tion, the reader is referred to 4.3.1 Writing. 19.4 Register Map The offset register address is relative to the registers base address. -
Page 660: Register Description
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5 Register Description 19.5.1 LETIMERn_CTRL - Control Register (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. - Page 661 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DEBUGRUN Debug Mode Run Enable Set to keep the LETIMER running in debug mode.
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Page 662: Letimern_Cmd - Command Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description TOGGLE LETn_O0 is toggled on CNT underflow. PULSE LETn_O0 is held active for one LFACLK clock cycle on CNT LETIMER0 underflow. The output then returns to its idle value as defined by OPOL0. -
Page 663: Letimern_Status - Status Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.3 LETIMERn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 664: Letimern_Comp0 - Compare Value Register 0 (Async Reg)
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x010 Reset Access Name Name... -
Page 665: Letimern_Rep0 - Repeat Counter Register 0 (Async Reg)
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) For More information about Registers please see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x018 Reset Access Name Name... -
Page 666: Letimern_If - Interrupt Flag Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.9 LETIMERn_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 667: Letimern_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.10 LETIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 668: Letimern_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 669: Letimern_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.12 LETIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 670: Letimern_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 671: Letimern_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 670... - Page 672 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8 OUT1LOC 0x00 I/O Location Decides the location of the LETIMER OUT1 pin...
- Page 673 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUT0LOC 0x00 I/O Location Decides the location of the LETIMER OUT0 pin...
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Page 674: Letimern_Prssel - Prs Input Select Register
EFM32JG1 Reference Manual LETIMER - Low Energy Timer 19.5.16 LETIMERn_PRSSEL - PRS Input Select Register Offset Bit Position 0x050 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 673... - Page 675 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:26 PRSCLEARMODE PRS Clear Mode Determines mode for PRS input clear...
- Page 676 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description PRSCH3 PRS Channel 3 selected as input PRSCH4 PRS Channel 4 selected as input PRSCH5 PRS Channel 5 selected as input PRSCH6 PRS Channel 6 selected as input...
- Page 677 EFM32JG1 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input...
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Page 678: Cryotimer - Ultra Low Energy Timer/Counter
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20. CRYOTIMER - Ultra Low Energy Timer/Counter Quick Facts What? 0 1 2 3 The CRYOTIMER is a timer capable of providing wakeup events/interrupts after deterministic intervals in all energy modes, including EM4. -
Page 679: Block Diagram
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.3.1 Block Diagram An overview of the CRYOTIMER is shown in Figure 20.1 CRYOTIMER Block Overview on page 678. LFXO CRYOCLK LFRCO Prescaler Counter ULFRCO Edge Detector Interrupt/ Wakeup Event OSCSEL... -
Page 680: Operation
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.3.2 Operation The desired low frequency oscillator for the CRYOTIMER operation can be selected by using OSCSEL in CRYOTIMER_CTRL. The selection must be made before enabling the CRYOTIMER, and it must be ensured that the selected oscillator is ready. This can be checked by observing LFXORDY or LFRCORDY (depending upon the oscillator selection) in CMU_STATUS. -
Page 681: Register Map
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CRYOTIMER_CTRL Control Register 0x004 CRYOTIMER_PERIODSEL Interrupt Duration 0x008 CRYOTIMER_CNT Counter Value 0x00C... -
Page 682: Register Description
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.5 Register Description 20.5.1 CRYOTIMER_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 683: Cryotimer_Periodsel - Interrupt Duration
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 682... - Page 684 EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIODSEL 0x20 Interrupts/Wakeup events period setting Defines the duration between the Interrupts/Wakeup events based on the pre-scaled clock.
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Page 685: Cryotimer_Cnt - Counter Value
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter Name Reset Access Description 20.5.3 CRYOTIMER_CNT - Counter Value Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:0 0x00000000 Counter Value These bits hold the Counter value. 20.5.4 CRYOTIMER_EM4WUEN - Wake Up Enable... -
Page 686: Cryotimer_If - Interrupt Flag Register
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.5.5 CRYOTIMER_IF - Interrupt Flag Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 687: Cryotimer_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 20.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 688: Acmp - Analog Comparator
EFM32JG1 Reference Manual ACMP - Analog Comparator 21. ACMP - Analog Comparator Quick Facts What? 0 1 2 3 The ACMP (Analog Comparator) compares two ana- log signals and returns a digital value telling which is greater. Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a cer- tain threshold. -
Page 689: Functional Description
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3 Functional Description An overview of the ACMP is shown in Figure 21.1 ACMP Overview on page 688 POSSEL VADIV VBDIV Warmup Interrupt Warm-up ACMPACT Counter DAC0 DAC1 Dedicated APORT0 APORT1 CSRESSEL APORT2... -
Page 690: Warm-Up Time
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3.1 Warm-up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL. The comparator requires some time to stabilize after it is enabled. This time period is called the warm-up time. The warm-up period is self-timed and will complete within 5µs after EN is set. -
Page 691: Hysteresis
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3.3 Hysteresis When the hysteresis level is set to a non-zero value, the digital output will not toggle until the positive input voltage is at a voltage equal to the hysteresis level above or below the negative input voltage (see Figure 21.3 Hysteresis on page 690... -
Page 692: Input Selection
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3.4 Input Selection The POSSEL and NEGSEL fields in ACMPn_INPUTSEL control the input connections to the positive and negative inputs of the compa- rator. The user can select external GPIO pins on the chip, or select a number of internal chip voltages. Pins are selected by configuring channels on APORT buses. - Page 693 EFM32JG1 Reference Manual ACMP - Analog Comparator ACMP Port APORT0 APORT1 APORT2 APORT3 APORT4 Polarity Shared Bus BUSAX BUSAY BUSBX BUSBY BUSCX BUSCY BUSDX BUSDY PD11 PD11 PD10 PD10 There are limitations on the POSSEL and NEGSEL connections than can be made. The user cannot select an X-bus for both POSSEL and NEGSEL simultaneously, nor a Y-bus for both POSSEL and NEGSEL simultaneously.
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Page 694: Capacitive Sense Mode
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3.5 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons. Such buttons are traces on the PCB laid out in a way that creates a parasitic capacitor between the button and the ground node. Because a human finger will have a small intrinsic capacitance to ground, the capacitance of the button will increase when the button is touched. -
Page 695: Interrupts And Prs Output
EFM32JG1 Reference Manual ACMP - Analog Comparator Voltage VADIV1 VADIV Divider VADIV0 voltage ACMPn_HYSTERESIS0.VADIV ACMPn_HSYTERESIS1.VADIV time ACMPOUT Figure 21.5. Capacitive Sensing Setup 21.3.6 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively. -
Page 696: Output To Gpio
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.3.7 Output to GPIO The output from the comparator and the capacitive sense output are available as alternate functions to the GPIO pins. Set the ACMP- PEN bit in ACMPn_ROUTE to enable the output to a pin and the LOCATION bits to select the output location. The GPIO-pin must also be set as output. -
Page 697: Register Description
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5 Register Description 21.5.1 ACMPn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 696... - Page 698 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description FULLBIAS Full Bias Current Set this bit to 1 for full bias current. See the datasheet for details. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 699 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description VREGVDD VREGVDD supply IOVDD0 IOVDD/IOVDD0 supply IOVDD1 IOVDD1 supply (if part has two I/O voltages) Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 700 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description INACTVAL Inactive Value The value of this bit is used as the comparator output when the comparator is inactive. Value Mode Description The inactive value is 0 HIGH The inactive state is 1 Reserved To ensure compatibility with future devices, always write bits to 0.
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Page 701: Acmpn_Inputsel - Input Selection Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.2 ACMPn_INPUTSEL - Input Selection Register Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 700... - Page 702 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSRESSEL Capacitive Sense Mode Internal Resistor Select These bits select the resistance value for the internal capacitive sense resistor. Resulting actual resistor values are given in the device datasheets.
- Page 703 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT2YCH2 APORT2Y Channel 2 APORT2YCH4 APORT2Y Channel 4 ..APORT2YCH30 0x1f APORT2Y Channel 30 APORT1XCH0 0x20 APORT1X Channel 0 APORT1YCH1 0x21...
- Page 704 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT2XCH3 0x43 APORT2X Channel 3 APORT2YCH4 0x44 APORT2Y Channel 4 APORT2XCH5 0x45 APORT2X Channel 5 ..APORT2YCH30 0x5e APORT2Y Channel 30...
- Page 705 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT0XCH15 0x0f Dedicated APORT0X Channel 15 APORT0YCH0 0x10 Dedicated APORT0Y Channel 0 APORT0YCH1 0x11 Dedicated APORT0Y Channel 1 APORT0YCH2 0x12 Dedicated APORT0Y Channel 2 ..
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Page 706: Acmpn_Status - Status Register
EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT4YCH4 0x84 APORT4Y Channel 4 APORT4XCH5 0x85 APORT4X Channel 5 ..APORT4YCH30 0x9e APORT4Y Channel 30 APORT4XCH31 0x9f APORT4X Channel 31... -
Page 707: Acmpn_If - Interrupt Flag Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.4 ACMPn_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 708: Acmpn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.6 ACMPn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 709: Acmpn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.7 ACMPn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 710: Acmpn_Aportreq - Aport Request Status Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.8 ACMPn_APORTREQ - APORT Request Status Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 711: Acmpn_Aportconflict - Aport Conflict Status Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x024 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 710... - Page 712 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0 1 if the bus connected to APORT4Y is in conflict with another pe-...
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Page 713: Acmpn_Hysteresis0 - Hysteresis 0 Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 714: Acmpn_Hysteresis1 - Hysteresis 1 Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 715: Acmpn_Routepen - I/O Routing Pine Enable Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 716: Acmpn_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual ACMP - Analog Comparator 21.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 715... - Page 717 EFM32JG1 Reference Manual ACMP - Analog Comparator Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUTLOC 0x00 I/O Location Decides the location of the OUT pin.
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Page 718: Adc - Analog To Digital Converter
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22. ADC - Analog to Digital Converter Quick Facts What? 0 1 2 3 The ADC is used to convert analog signals into a digital representation and features low-power, auton- omous operation. -
Page 719: Features
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.2 Features • Programmable resolution (6/8/12-bit) • 13 conversion clock cycles for a 12-bit conversion • Maximum 1 Msps @ 12-bit • Maximum 1.6 Msps @ 6-bit • Configurable acquisition time •... -
Page 720: Functional Description
EFM32JG1 Reference Manual ADC - Analog to Digital Converter • Support for offset and gain calibration • Interrupt generation and/or DMA request when • Programmable number of converted data available in the single FIFO (also generates DMA request) • Programmable number of converted data available in the scan FIFO (also generates DMA request) •... -
Page 721: Clock Selection
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.1 Clock Selection The ADC logic is partitioned into two clock domains: HFPERCLK and ADC_CLK. The HFPERCLK domain contains the register inter- face logic, APORT request logic and portions of FIFO read logic. The HFPERCLK is the default clock for the ADC peripheral. The rest of the ADC is clocked by the ADC_CLK domain. -
Page 722: Adc Modes
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.3 ADC Modes The ADC contains two programmable modes: single channel mode and scan mode. Both modes have separate configuration registers and a four-deep FIFO for conversion results. Both modes may be set up to run only once per trigger or to automatically repeat after each operation. -
Page 723: Warm-Up Time
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.4 Warm-up Time After power-on, the ADC requires some time for internal bias currents and references to settle prior to starting a conversion. This time period is called the warm-up time. Warm-up timing is performed by hardware. Software must program the number of ADC_CLK cycles required to count at least 1 µs in the TIMEBASE field of the ADCn_CTRL register. - Page 724 EFM32JG1 Reference Manual ADC - Analog to Digital Converter ADC standby/ slowacc ADC warm-up ADC conversion WARMUPMODE Conversion trigger Conversion trigger ADC warmed up waiting for trigger Power NORMAL 5 µs Time 1 µs Power KEEPINSTANDBY/ KEEPINSLOWACC 5 µs 5 µs Time 1 µs...
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Page 725: Input Selection
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.5 Input Selection The ADC samples and converts the analog voltage differential at its positive and negative voltage inputs. The input multiplexers of the ADC can connect these inputs to one of several internal nodes (e.g., temperature sensor) or to external signals via analog ports (APORT0, APORT1, APORT2, APORT3 or APORT4). - Page 726 EFM32JG1 Reference Manual ADC - Analog to Digital Converter The mapping for external I/O connections to ADC0 inputs is shown in Table 22.1 ADC0 Bus and Pin Mapping on page 725. Note that this table shows the mapping for an entire family of devices. Refer to the Pin Definition and the APORT Client Map in the device datasheet for specific details on which I/O are available for each family and package configuration.
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Page 727: Configuring Adc Inputs In Single Channel Mode
EFM32JG1 Reference Manual ADC - Analog to Digital Converter Multiple peripherals may request the same shared system bus (BUSAX, BUSAY, BUSBX, etc.). When this happens, a conflict status is generated and that bus is kept floating. If this happens with the ADC, the PROGERR field in ADCn_STATUS is set to BUSCONF, and an interrupt may be generated (if enabled). -
Page 728: Configuring Adc Inputs In Scan Mode
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.5.2 Configuring ADC Inputs in Scan Mode In scan mode, the ADC can sample and convert up to 32 external channels on each conversion trigger. Internal channels are not avail- able in scan mode. The ADC's scanner logic automatically changes the input mux settings between conversions, eliminating the need for firmware intervention. - Page 729 EFM32JG1 Reference Manual ADC - Analog to Digital Converter SCANINPUTSEL APORT1CH16TO23 APORT1CH16TO23 APORT4CH8TO15 APORT1CH16TO23 APORT-Channel (Positive) APORT-Channel (Negative) I/O Differential SCANMASK SCANINPUTID Figure 22.7. ADC Differential Scan Mode Example In certain applications it may be desirable to perform differential conversions on several channels against a common voltage. The ADCn_SCANNEGSEL register allows eight of the SCANINPUTIDs to re-map the negative terminal of a differential conversion to a common channel.
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Page 730: Aport Conflicts
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.5.3 APORT Conflicts The ADC shares common analog buses connected to its APORTs (1-4) with other analog peripherals (see Table 22.1 ADC0 Bus and Pin Mapping on page 725). As the ADC performs single or scan conversions, it requests the shared buses and sends selections for the control switches to connect the desired I/O pins. -
Page 731: Advanced Full-Scale Voltage Configuration
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.6.2 Advanced Full-Scale Voltage Configuration For most applications, the pre-defined VFS options described in 22.3.6.1 Basic Full-Scale Voltage Configuration are suitable. Advanced VFS configurations are also possible by programming the REF bitfield in ADCn_SINGLECTRL or ADCn_SCANCTRL to the CONF op- tion. -
Page 732: Programming Of Bias Current
EFM32JG1 Reference Manual ADC - Analog to Digital Converter The maximum and minimum input voltage which the ADC can recognize at any external pin is limited to the supply voltages. If VFS is configured to be larger than the supply range, the full ADC range will not be available. For example, with a 3.3 V supply and VFS con- figured to 5 V, the input voltage for single-ended conversions will be limited to 0 to 3.3 V, though the effective VFS is still 5 V. -
Page 733: Conversion Tailgating
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.8.1 Conversion Tailgating Scan conversions have priority over single channel conversions. This means that if scan and single triggers are received simultaneous- ly, or even if the scan is received later when ADC is being warmed up for performing a single conversion, the scan conversion will have priority and will be done before the single conversion. -
Page 734: Conversion Trigger
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.8.3 Conversion Trigger The conversion modes can be activated by writing a 1 to the SINGLESTART or SCANSTART bit in the ADCn_CMD register. The con- versions can be stopped by writing a 1 to the SINGLESTOP or SCANSTOP bit in the ADCn_CMD register. A START command will have priority over a STOP command. -
Page 735: Output Results
EFM32JG1 Reference Manual ADC - Analog to Digital Converter already running before ADC sends out the clock request. If AUXHFRCO is chosen as the ADC clock source, and it is not already run- ning, then the CMU automatically turns it on when the ADC sends a clock request. In such a case, it takes (7 ADC_CLK cycles + the oscillator startup time) for the ADC_CLK to start. -
Page 736: Resolution
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.8.5 Resolution The ADC performs 12-bit conversions by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conver- sion by selecting a lower resolution (6 or 8 bits). For more information on the accuracy of the ADC, the reader is referred to the electri- cal characteristics section for the device. -
Page 737: Adjustment
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.8.7 Adjustment By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read as 0. By setting ADJ in ADCn_SINGLECTRL/ ADCn_SCANCTRL, the results are left adjusted as shown in Table 22.6 ADC Results Representation on page... -
Page 738: Adc As A Random Number Generator
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.8.10 ADC as a Random Number Generator The ADC can be used as a random number generator. This is done by: 1. Choose the REF in the ADCn_SINGLECTRL as CONF, setting the VREFSEL in the ADCn_SINGLECTRLX as VENTROPY and VINATT in the same register to its maximum value of 15. -
Page 739: Offset Calibration
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.11.1 Offset Calibration Offset calibration must be performed prior to gain calibration. Follow these steps for the offset calibration in single mode: 1. Select the desired full scale configuration by setting the REF bit field of the ADCn_SINGLECTRL register. -
Page 740: Em2 Or Em3 Operation
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.12 EM2 or EM3 Operation The ADC can operate in EM2 or EM3 mode. For EM2 or EM3 operation the ADC_CLK must be selected as AUXHFRCO. The section 22.3.1 Clock Selection describes how to choose AUXHFRCO as the ADC_CLK. -
Page 741: Adc Programming Model
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.3.15 ADC Programming Model The ADC configuration registers are considered static and can only be updated when (1) ADC is in SYNC mode and (2) ADC is idle. ADC is considered busy when it is doing conversions (either the SINGLEACT or SCANACT status flag is high) or when it is warmed up (one of the following status flags is high: WARM, SINGLEREFWARM, SCANREFWARM). -
Page 742: Register Map
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x008 ADCn_CMD Command Register 0x00C ADCn_STATUS Status Register 0x010... -
Page 743: Register Description
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5 Register Description 22.5.1 ADCn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 742... - Page 744 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CHCONMODE Channel Connect Selects Channel Connect Mode Value...
- Page 745 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Value Description PRESC Clock prescale factor. ADC_CLK is divided by (PRESC+1) to produce adc_clk_sar. ADCCLKMODE ADC Clock Mode Selects ADC_CLK source as synchronous or asynchronous - with respect to the Peripheral Clock (HFPERCLK).
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Page 746: Adcn_Cmd - Command Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Select Warm-up Mode for ADC Value Mode Description NORMAL ADC is shut down after each conversion. 5us warmup time is used be- fore each conversion. KEEPINSTANDBY ADC is kept in standby mode between conversions. 1us warmup time is used before each conversion. -
Page 747: Adcn_Status - Status Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.3 ADCn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 748: Adcn_Singlectrl - Single Channel Control Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.4 ADCn_SINGLECTRL - Single Channel Control Register Offset Bit Position 0x010 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 747... - Page 749 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description CMPEN Compare Logic Enable for Single Channel Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 750 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT0YCH0 Select APORT0YCH0 APORT0YCH1 Select APORT0YCH1 APORT0YCH15 Select APORT0YCH15 APORT1XCH0 Select APORT1XCH0 APORT1YCH1 Select APORT1YCH1 ..APORT1YCH31 Select APORT1YCH31 APORT2YCH0 Select APORT2YCH0 APORT2XCH1 Select APORT2XCH1 ..APORT2XCH31...
- Page 751 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT2YCH0 Select APORT2YCH0 APORT2XCH1 Select APORT2XCH1 ..APORT2XCH31 Select APORT2XCH31 APORT3XCH0 Select APORT3XCH0 APORT3YCH1 Select APORT3YCH1 ..APORT3YCH31 Select APORT3YCH31 APORT4YCH0 Select APORT4YCH0 APORT4XCH1 Select APORT4XCH1 ..
- Page 752 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description EXTSINGLE Single ended external reference 2XEXTDIFF Differential external reference, 2x 2XVDD VFS = 2xAVDD with AVDD as the reference source CONF Use SINGLECTRLX to configure reference Single Channel Resolution Select Select single channel conversion resolution.
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Page 753: Adcn_Singlectrlx - Single Channel Control Register Continued
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.5 ADCn_SINGLECTRLX - Single Channel Control Register continued Offset Bit Position 0x014 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 752... - Page 754 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CONVSTARTDELAY- Enable delaying next conversion start Delay value for next conversion start event.
- Page 755 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description TIMED Single channel trigger should be a pulse long enough to provide the re- quired warm-up time for the selected ADC warmup mode. The negative edge requests sample acquisition. DELAY can be used to delay the warm-up request if the pulse is too long.
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Page 756: Adcn_Scanctrl - Scan Control Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.6 ADCn_SCANCTRL - Scan Control Register Offset Bit Position 0x018 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 755... - Page 757 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description CMPEN Compare Logic Enable for Scan Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 758 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 2XEXTDIFF Differential external reference, 2x 2XVDD VFS=2xAVDD with AVDD as the reference source CONF Use SCANCTRLX to configure reference Scan Sequence Resolution Select Select scan sequence conversion resolution.
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Page 759: Adcn_Scanctrlx - Scan Control Register Continued
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.7 ADCn_SCANCTRLX - Scan Control Register continued Offset Bit Position 0x01C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 758... - Page 760 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CONVSTARTDELAY- Enable delaying next conversion start Delay value for next conversion start event.
- Page 761 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description TIMED Scan trigger should be a pulse long enough to provide the required warm-up time for the selected ADC warmup mode. The negative edge requests sample acquisition. DELAY can be used to delay the warm-up request if the pulse is too long.
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Page 762: Adcn_Scanmask - Scan Sequence Input Mask Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register Offset Bit Position 0x020 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 761... - Page 763 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:0 SCANINPUTEN 0x00000000 Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included in scan sequence in either single ended or differential mode.
- Page 764 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT9INPUT9NEG- xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT9 Negative input: chosen by IN- x1xxxxxxxxx PUT9NEGSEL) included in mask INPUT10INPUT11 xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT10 Negative input: ADCn_INPUT11) in- 1xxxxxxxxxx cluded in mask...
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Page 765: Adcn_Scaninputsel - Input Selection Register For Scan Mode
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.9 ADCn_SCANINPUTSEL - Input Selection register for Scan mode Offset Bit Position 0x024 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 764... - Page 766 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24 INPUT24TO31SEL 0x00 Inputs chosen for ADCn_INPUT24-ADCn_INPUT31 as referred in...
- Page 767 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 12:8 INPUT8TO15SEL 0x00 Inputs chosen for ADCn_INPUT8-ADCn_INPUT15 as referred in SCANMASK Mode Value Description APORT0CH0TO7 Select APORT0's CH0-CH7 as ADCn_INPUT8-ADCn_INPUT15 APORT0CH8TO15 Select APORT0's CH8-CH15 as ADCn_INPUT8-ADCn_INPUT15 APORT1CH0TO7...
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Page 768: Adcn_Scannegsel - Negative Input Select Register For Scan
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.10 ADCn_SCANNEGSEL - Negative Input select register for Scan Offset Bit Position 0x028 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 767... - Page 769 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:14 INPUT15NEGSEL Negative Input select Register for ADCn_INPUT15 in Differential...
- Page 770 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Value Mode Description INPUT1 Selects ADCn_INPUT1 as negative channel input INPUT3 Selects ADCn_INPUT3 as negative channel input INPUT5 Selects ADCn_INPUT5 as negative channel input INPUT7 Selects ADCn_INPUT7 as negative channel input...
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Page 771: Adcn_Cmpthr - Compare Threshold Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.11 ADCn_CMPTHR - Compare Threshold Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 ADGT 0x0000 Greater Than Compare Threshold Compare threshold value for greater-than comparison. Must match the conversion data representation chosen. -
Page 772: Adcn_Biasprog - Bias Programming Register For Various Analog Blocks Used In Adc Operation
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.12 ADCn_BIASPROG - Bias Programming Register for various analog blocks used in ADC operation. Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 773: Adcn_Cal - Calibration Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.13 ADCn_CAL - Calibration Register Offset Bit Position 0x034 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 772... - Page 774 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description CALEN Calibration mode is enabled When enabled, the adc performs conversion and sends raw data to the ADC fifos. This can also be used to debug the adc...
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Page 775: Adcn_If - Interrupt Flag Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.14 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x038 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 774... - Page 776 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PROGERR Programming Error Interrupt Flag Indicates that a programming error has occurred. Read the STATUS register for cause.
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Page 777: Adcn_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.15 ADCn_IFS - Interrupt Flag Set Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 778: Adcn_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.16 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 779: Adcn_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.17 ADCn_IEN - Interrupt Enable Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 780: Adcn_Singledata - Single Conversion Result Data (Actionable Reads)
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 Single Conversion Result Data This register holds the results from the last single channel mode conversion. Reading this field pops one entry from the SINGLE FIFO. -
Page 781: Adcn_Singledatap - Single Conversion Result Data Peek Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Single Conversion Result Data Peek The register holds the results from the last single channel mode conversion. Reading this field will not pop an entry from the SINGLE FIFO. -
Page 782: Adcn_Scandatax - Scan Sequence Result Data + Data Source Register (Actionable Reads)
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads) Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 783: Adcn_Aportreq - Aport Request Status Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.24 ADCn_APORTREQ - APORT Request Status Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 784: Adcn_Aportconflict - Aport Conflict Status Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x080 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 783... - Page 785 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0 1 if the bus connected to APORT4Y is in conflict with another pe-...
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Page 786: Adcn_Singlefifocount - Single Fifo Count Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 787: Adcn_Singlefifoclear - Single Fifo Clear Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 788: Adcn_Aportmasterdis - Aport Bus Master Disable Register
EFM32JG1 Reference Manual ADC - Analog to Digital Converter 22.5.30 ADCn_APORTMASTERDIS - APORT Bus Master Disable Register Offset Bit Position 0x094 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 787... - Page 789 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YMASTER- APORT4Y Master Disable Determines if the ADC will request this APORT bus (if selected by POSSEL or NEGSEL or SCANINPUTSEL). When 1, ADC only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored.
- Page 790 EFM32JG1 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Value Description APORT mastering enabled APORT mastering disabled APORT2XMASTER- APORT2X Master Disable Determines if the ADC will request this APORT bus (if selected by POSSEL or NEGSEL or SCANINPUTSEL). When 1, ADC only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored.
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Page 791: Idac - Current Digital To Analog Converter
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23. IDAC - Current Digital to Analog Converter Quick Facts What? 0 1 2 3 The IDAC can sink or source a configurable con- stant current. Why? The IDAC can be used to bias external circuits or (in... -
Page 792: Functional Description
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.3 Functional Description An overview of the IDAC module is shown in Figure 23.1 IDAC Overview on page 791. The IDAC is designed to source or sink a programmable current which can be controlled by setting the range and the step in the RANGESEL and STEPSEL bitfields in IDAC_CURRPROG register. -
Page 793: Output Control
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.3.3 Output Control The IDAC output to APORT can be controlled either by software or PRS. After configuring the desired output mode, set APORTOU- TENPRS in IDAC_CTRL to enable PRS control over the output, or set APORTOUTEN in IDAC_CTRL to enable the output via soft- ware. -
Page 794: Aport Configuration
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.3.5 APORT Configuration The IDAC output is routed to a pin through the APORT system. The IDAC can be in either master or slave mode when connecting to the APORT. By default the IDAC is in master mode and will drive the channel selected. To enable slave mode, set APORTMASTERDIS in IDAC_CTRL. -
Page 795: Interrupts
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter IDAC Port APORT1 Polarity Shared Bus BUSCX BUSCY PD15 PD14 PD13 PD12 PD11 PD10 23.3.6 Interrupts The APORTCONFLICT interrupt flag in the IDAC_IF register indicates that a conflict has occurred when requesting a channel from the APORT. -
Page 796: Prs Triggered Charge Injection
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.3.11 PRS Triggered Charge Injection The amount of charge sourced or sunk by the IDAC can be controlled by the PRS (e.g., using a timer as producer) via the output switch. -
Page 797: Register Description
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5 Register Description 23.5.1 IDAC_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 796... - Page 798 EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:20 PRSSEL IDAC Output PRS channnel Select Selects which PRS channel to use, when OUTENPRS is set.
- Page 799 EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter Name Reset Access Description Selects the power source for the IDAC Value Mode Description AVDD IOVDD 11:4 APORTOUTSEL 0x00 APORT Output Select Select output mode. APORT1XCH0 0x20 APORT1X Channel 0...
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Page 800: Idac_Curprog - Current Programming Register
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5.2 IDAC_CURPROG - Current Programming Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 801: Idac_Dutyconfig - Duty Cycle Configauration Register
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5.3 IDAC_DUTYCONFIG - Duty Cycle Configauration Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 802: Idac_If - Interrupt Flag Register
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5.5 IDAC_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 803: Idac_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5.7 IDAC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 804: Idac_Aportreq - Aport Request Status Register
EFM32JG1 Reference Manual IDAC - Current Digital to Analog Converter 23.5.9 IDAC_APORTREQ - APORT Request Status Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 805: Gpcrc - General Purpose Cyclic Redundancy Check
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24. GPCRC - General Purpose Cyclic Redundancy Check Quick Facts What? 0 1 2 3 The GPCRC is an error-detecting module commonly used in digital networks and storage systems to de- tect accidental changes to data. -
Page 806: Functional Description
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.3 Functional Description An overview of the GPCRC module is shown in Figure 24.1 GPCRC Overview on page 805. GPCRC Module RDATA word or byte bit reversal DATA INPUTDATA byte... -
Page 807: Polynomial Specification
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.3.1 Polynomial Specification POLYSEL in GPCRC_CTRL selects between 32-bit and 16-bit polynomial functions. When a 32-bit polynomial is selected, the fixed IEEE 802.3 polynomial(0x04C11DB7) is used. When a 16-bit polynomial is selected, any valid polynomial can be defined by the user in GPCRC_POLY. -
Page 808: Byte-Level Bit Reversal And Byte Reordering
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.3.5 Byte-Level Bit Reversal and Byte Reordering The byte-level bit reversal and byte reordering operations occur before the data is used in the CRC calculation. Byte reordering can occur on words or half words. The hardware ignores the BYTEREVERSE field with any byte writes or operations with byte mode ena- bled (BYTEMODE = 1), but the bit reversal settings (BITREVERSE) are still applied to the byte. - Page 809 EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Byte 3 Byte 2 Byte 1 Byte 0 Input data is little endian, MSB-first BYTEREVERSE bits set for byte reversal 8'h00 8'h00 Byte 0 Byte 1 BITREVERSE bit set for byte-...
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Page 810: Register Map
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Original CRC Calculation Method Equivalent Settings Input to CRC calculation Polynomial Byte Order Bit Order(MSB/LSB BYTEREVERSE BITREVERSE Width(bits) first) Setting Setting Notes: 1. X indicates a "don't care". 2. Bn is the byte field within the word. -
Page 811: Register Description
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5 Register Description 24.5.1 GPCRC_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 810... - Page 812 EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions AUTOINIT Auto Init Enable Enables auto init by re-seeding the CRC result based on the value in INIT after reading of DATA, DATAREV or DATABY- TEREV.
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Page 813: Gpcrc_Cmd - Command Register
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5.2 GPCRC_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 814: Gpcrc_Poly - Crc Polynomial Value
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5.4 GPCRC_POLY - CRC Polynomial Value Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 815: Gpcrc_Inputdatahword - Input 16-Bit Data Register
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 816: Gpcrc_Data - Crc Data Register
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5.8 GPCRC_DATA - CRC Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 CRC Data Register CRC Data Register, read only. The CRC data register may still be indirectly written from software, by writing the INIT regis- ter and then issue an INITIALIZE command. -
Page 817: Gpcrc_Databyterev - Crc Data Byte Reverse Register
EFM32JG1 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 24.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 DATABYTEREV 0x00000000 Data Byte Reverse Value Byte reversed version of CRC Data register. When a 32-bit CRC polynomial is selected, the bytes are swizzled to {B0, B1, B2, B3}. -
Page 818: Crypto - Crypto Accelerator
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25. CRYPTO - Crypto Accelerator Quick Facts What? 0 1 2 3 A fast and energy efficient autonomous hardware accelerator for AES encryption and decryption with 128- or 256-bit keys, ECC over prime and binary Galois finite fields, SHA-1, SHA-224 and SHA-256. -
Page 819: Features
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.2 Features • Efficient AES core • Encryption/decryption using 128-bit key (54 clock cycles) or 256-bit key (75 clock cycles) • Key buffer • Supports autonomous cipher block modes (e.g. ECB, CTR, CBC, PCBC, CFB, CBC-MAC, GMAC, CCM, CCM* and GCM) across multiple blocks •... -
Page 820: Functional Description
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4 Functional Description A block diagram of the CRYPTO module is shown in Figure 25.1 CRYPTO Overview on page 819. AHB bus Sequencer Control DATA TRANSFER DDATA0[255:0] DDATA0[255:0] QDATA0[511:0] KEY[255:0] DDATA1[255:0] DATA1[127:0] DATA0[127:0]... -
Page 821: Data And Key Registers
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.1 Data and Key Registers The CRYPTO module contains five 256-bit registers. Accelerators are implemented through instructions operating on these registers, either by copying data between registers and external components like through DMA, or by executing instructions on the registers. -
Page 822: Data0 Zero
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Shift on write and read DATA0 (128 bit) CRYPTO_DATA0 CRYPTO_XORDATA0 Write data Read data CRYPTO_DATA0BYTE CRYPTO_XORDATA0BYTE DATA1 (128 bit) CRYPTO_DATA1 Write data Read data CRYPTO_DATA1BYTE0 DATA2 (128 bit) CRYPTO_DATA2 Write data Read data... -
Page 823: Ddata0 And Ddata1 Quick Observation
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.1.2 DDATA0 and DDATA1 Quick Observation DDATA0LSBS in CRYPTO_DSTATUS shows the 4 least significant bits in DDATA0. DDATA0MSBS in CRYPTO_DSTATUS shows the 4 most significant bits of DDATA0, while DDATA1MSB in CRYPTO_DSTATUS shows the msb of DDATA1. These observation bitfields are useful for determining the sign of the value in the data registers without having to read out the full register data register values The 4 bits observed by DDATA0MSBS will change depending on RESULTWIDTH in CRYPTO_WAC. -
Page 824: Available Instructions
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.2.2 Available Instructions The available ALU instructions are listed in Table 25.1 ALU Instructions on page 823, data transfer instructions are listed in Table 25.2 Transfer Instructions on page 824, conditional instructions are listed in Table 25.3 Conditional Instructions on page 824... - Page 825 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Instruction Description Constraints/Notes SHRA DDATA0 = V0 >> 1 | V0[resultwidth-1] << resultwidth-1 DDATA0 = 0 DDATA0 = V0 ^ V1 If V0 != DDATA0, then V1 != DDATA0 DDATA0 = ~V0 CSET...
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Page 826: Mulx Details
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Instruction Operation Constraints EXECIFB Execute following instructions if in part B of sequence EXECIFNLAST Execute following instructions if not in last iteration of sequence EXECIFLAST Execute following instructions if in last itera- tion of sequence... -
Page 827: Carry
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.2.6 Carry The carry output from most instructions can be observed through CARRY in CRYPTO_DSTATUS. Shift-instructions set CARRY to the value that is shifted out of the register, addition and multiplication set it on register overflow, and subtraction sets it on borrow, e.g. un- derflow. -
Page 828: Aes
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.4 AES The AES core operates on data in the 128-bit register DATA0 using the either a 128-bit or 256-bit key from the KEY register. The key width is specified by AES256 in CRYPTO_CTRL. AES operations are implemented as the AESENC and AESDEC instructions, for AES encryption and AES decryption respectively. - Page 829 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator DATA KEY/KEYBUF [7:0] [15:8] [23:16] [31:24] Figure 25.5. CRYPTO Data and Key Orientation as Defined in the Advanced Encryption Standard silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 828...
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Page 830: Sha
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.5 SHA The CRYPTO SHA instruction implements SHA-1 with a 160-bit digest or SHA-2 with a 224-bit digest (SHA-224) or 256-bit digest (SHA-256). Depending on SHAMODE in CRYPTO_CTRL, SHA-1, SHA-224 or SHA-256 will be run on the data in QDATA1, and the result will be put on DDATA0. -
Page 831: Gcm And Gmac
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.7 GCM and GMAC CRYPTO implements support for Galois/Counter Mode (GCM), and also Galois Message Authentication Code (GMAC), by providing AES instructions and allowing multiplication on the field GF(2^128) defined by the polynomial x^128 + x^7 + x^2 + x + 1. -
Page 832: Dma Initial Bytes Skip
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.8.1 DMA Initial Bytes Skip The DMA must be configured to use 32-bit transfer size. This normally would imply that the source data must be aligned to a 4 byte address boundry. However, it is possible to skip the intial bytes (1 to 3) when using DMA to write to DATA0 or DATA1 through a CRYP- TO instruction operation. -
Page 833: Example: Cipher Block Chaining (Cbc)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.4.11 Example: Cipher Block Chaining (CBC) In the following the setup and operation of CBC is explained and illustrated. The example can easily be adjusted to perform other cipher block modes. silabs.com | Smart. Connected. Energy-friendly. -
Page 834: Register Map
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CRYPTO_CTRL Control Register 0x004 CRYPTO_WAC Wide Arithmetic Configuration 0x008 CRYPTO_CMD Command Register 0x010 CRYPTO_STATUS... - Page 835 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Offset Name Type Description 0x110 CRYPTO_DDATA4 RWH(nB)(a) DDATA4 Register Access 0x130 CRYPTO_DDATA0BIG RWH(nB)(a) DDATA0 Register Big Endian Access 0x140 CRYPTO_DDATA0BYTE RWH(nB)(a) DDATA0 Register Byte Access 0x144 CRYPTO_DDATA1BYTE RWH(nB)(a) DDATA1 Register Byte Access 0x148...
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Page 836: Register Description
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6 Register Description 25.6.1 CRYPTO_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 835... - Page 837 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description COMBDMA0WEREQ 0 Combined Data0 Write DMA Request When cleared, the DATA0WR and DATA0XORWR operate independently. When set, DATA0XORWR requests are also giv- en through DATA0WR Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-...
- Page 838 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description Value Mode Description FULL Target register is fully read/written during every DMA transaction LENLIMIT Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read.
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Page 839: Crypto_Wac - Wide Arithmetic Configuration
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.2 CRYPTO_WAC - Wide Arithmetic Configuration Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 838... - Page 840 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:10 RESULTWIDTH Result Width Result-size for non-modulus instructions Value Mode...
- Page 841 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description ECCBIN163KN P modulus for K-163 ECC curve ECCPRIME256N P modulus for P-256 ECC curve ECCPRIME224N P modulus for P-224 ECC curve ECCPRIME192N P modulus for P-192 ECC curve silabs.com | Smart. Connected. Energy-friendly.
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Page 842: Crypto_Cmd - Command Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.3 CRYPTO_CMD - Command Register Offset Bit Position 0x008 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 841... - Page 843 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SEQSTEP Sequence Step When in a halted sequence, executes the current instruction and moves to the next...
- Page 844 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description SHRB DDATA0 = V0 >> 1 | V0[0] << resultwidth-1 SHR1 DDATA0 = V0 >> 1 | 1 << resultwidth-1 ADDO DDATA0 = V0 + V1 ADDIC DDATA0 = V0 + V1 + carry << 128...
- Page 845 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description DATATODMA0 DMA = DATAX, for DATAX = DATA0, DDATA0, DDATA0BIG or QDA- DATA0TOBUF BUFC = DATA0. BUFC buffer defined in WRITEBUFSEL in CRYP- TO_CTRL. DATA0TOBUFXOR BUFC = BUFC ^ DATA0. BUFC buffer defined in WRITEBUFSEL in CRYPTO_CTRL.
- Page 846 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description DDATA3TODDATA0 DDATA0 = DDATA3 DDATA3TODDATA1 DDATA1 = DDATA3 DDATA3TODDATA2 DDATA2 = DDATA3 DDATA3TODDATA4 DDATA4 = DDATA3 DDATA3LTODATA0 DATA0 = DDATA3[127:0] DDATA3HTODATA1 DATA1 = DDATA3[255:128] DDATA4TODDATA0 DDATA0 = DDATA4 DDATA4TODDATA1...
- Page 847 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description SELDDATA1DDATA2 Use DDATA1 as V0, DDATA2 as V1 SELDDATA2DDATA2 Use DDATA2 as V0, DDATA2 as V1 SELDDATA3DDATA2 Use DDATA3 as V0, DDATA2 as V1 SELDDATA4DDATA2 Use DDATA4 as V0, DDATA2 as V1...
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Page 848: Crypto_Status - Status Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description SELDATA1DATA1 Use DATA1 as V0, DATA1 as V1 SELDATA2DATA1 Use DATA2 as V0, DATA1 as V1 EXECIFA Run following if in A sequence EXECIFB Run following if in B sequence... -
Page 849: Crypto_Dstatus - Data Status Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.5 CRYPTO_DSTATUS - Data Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 850: Crypto_Cstatus - Control Status Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.6 CRYPTO_CSTATUS - Control Status Register Offset Bit Position 0x018 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 849... - Page 851 EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 24:20 SEQIP 0x00 Sequence Next Instruction Pointer Next sequence instruction when in halted sequence...
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Page 852: Crypto_Key - Key Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator Name Reset Access Description DATA2 25.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 0xXXXXXXX Key Access Access the KEY. 4x32bits (8x32bits if AES256 in CRYPTO_CTRL is set) read/write accesses are required to fully read/write KEY. -
Page 853: Crypto_Seqctrl - Sequence Control
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.9 CRYPTO_SEQCTRL - Sequence Control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description HALT Halt Sequence Allows stepping through CRYPTO instructions in the sequence for debugging. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 854: Crypto_Seqctrlb - Sequence Control B
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.10 CRYPTO_SEQCTRLB - Sequence Control B Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 855: Crypto_Ifs - Interrupt Flag Set Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.12 CRYPTO_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 856: Crypto_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.13 CRYPTO_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 857: Crypto_Ien - Interrupt Enable Register
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.14 CRYPTO_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 858: Crypto_Seq1 - Sequence Register 1
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.16 CRYPTO_SEQ1 - Sequence Register 1 Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:24 INSTR7 0x00 Sequence Instruction 7 Sequence instruction. See INSTR the CRYPTO_CMD for a possible values. -
Page 859: Crypto_Seq3 - Sequence Register 3
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.18 CRYPTO_SEQ3 - Sequence Register 3 Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:24 INSTR15 0x00 Sequence Instruction 15 Sequence instruction. See INSTR the CRYPTO_CMD for a possible values. -
Page 860: Crypto_Data0 - Data0 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:0 DATA0 0xXXXXXXX Data 0 Access Access to DATA0. 4x32bits read/write accesses are required to fully read/write DATA0 25.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads) -
Page 861: Crypto_Data2 - Data2 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:0 DATA2 0xXXXXXXX Data 2 Access Access to DATA2. 4x32bits read/write accesses are required to fully read/write DATA2. -
Page 862: Crypto_Data0Xor - Data0Xor Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:0 DATA0XOR 0xXXXXXXX XOR Data 0 Access Any value written to this register will be XOR'ed with the value of DATA0. The result is stored in DATA0. Reads return DA- TA0 directly. -
Page 863: Crypto_Data1Byte - Data1 Register Byte Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 864: Crypto_Data0Byte12 - Data0 Register Byte 12 Access (No Bit Access)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access) Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 865: Crypto_Data0Byte14 - Data0 Register Byte 14 Access (No Bit Access)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access) Offset Bit Position 0x0C8 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 866: Crypto_Ddata0 - Ddata0 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:0 DDATA0 0xXXXXXXX Double Data 0 Access Access to DDATA0. 8x32bits read/write accesses are required to fully read/write DDATA0. -
Page 867: Crypto_Ddata2 - Ddata2 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:0 DDATA2 0xXXXXXXX Double Data 0 Access Access to DDATA2, which consists of {DATA1, DATA0}. 8x32bits read/write accesses are required to fully read/write DDA- TA2. -
Page 868: Crypto_Ddata4 - Ddata4 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x110 Reset Access Name Name Reset Access Description 31:0 DDATA4 0xXXXXXXX Double Data 0 Access Access to DDATA4, which is equal to the full width of KEYBUF regardless of AES256 in CRYPTO_CTRL. 8x32bits read/ write accesses are required to fully read/write DDATA4. -
Page 869: Crypto_Ddata0Byte - Ddata0 Register Byte Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.38 CRYPTO_DDATA0BYTE - DDATA0 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 870: Crypto_Ddata0Byte32 - Ddata0 Register Byte 32 Access. (No Bit Access)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.40 CRYPTO_DDATA0BYTE32 - DDATA0 Register Byte 32 access. (No Bit Access) Offset Bit Position 0x148 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 871: Crypto_Qdata1 - Qdata1 Register Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.42 CRYPTO_QDATA1 - QDATA1 Register Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x184 Reset Access Name Name Reset Access Description 31:0 QDATA1 0xXXXXXXX Quad Data 1 Access Access to QDATA1, which is equal to {DATA3, DATA2, DATA1, DATA0} and {DDATA3, DDATA2}. 16x32bits read/write ac- cesses are required to fully read/write QDATA1. -
Page 872: Crypto_Qdata0Byte - Qdata0 Register Byte Access (No Bit Access) (Actionable Reads)
EFM32JG1 Reference Manual CRYPTO - Crypto Accelerator 25.6.44 CRYPTO_QDATA0BYTE - QDATA0 Register Byte Access (No Bit Access) (Actionable Reads) Offset Bit Position 0x1C0 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 873: Gpio - General Purpose Input/Output
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26. GPIO - General Purpose Input/Output Quick Facts What? 0 1 2 3 The General Purpose Input/Output (GPIO) is used for pin configuration, direct pin manipulation and sensing, as well as routing for peripheral pin connec- tions. -
Page 874: Features
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.2 Features • Individual configuration for each pin • Tristate (reset state) • Push-pull • Open-drain • Pull-up resistor • Pull-down resistor • Drive strength • 1 mA • 10 mA • Slewrate •... -
Page 875: Functional Description
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3 Functional Description An overview of the GPIO module is shown in Figure 26.1 Pin Configuration on page 874.The GPIO pins are grouped into 16-pin ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,..,15). Fewer than 16 bits may be available on some ports, depending on the total number of I/O pins on the package. -
Page 876: Pin Configuration
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.1 Pin Configuration In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15. - Page 877 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Filter enable Optional Input enable pull-up Glitch suppression filter Optional Analog connections pull-down Figure 26.2. Tristated Output with Optional Pull-up or Pull-down When MODEn is PUSHPULL or PUSHPULLALT, the pin operates in push-pull mode. In this mode, the pin can have alternate port con- trol values and can be driven either high or low, dependent on the value of GPIO_Px_DOUT.
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Page 878: Over Voltage Tolerance
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.1.1 Over Voltage Tolerance Over voltage capability is available for most pins. If available, it allows the pin to be used at either the minimum of VDDIO + 2V and 5.5V (for 5V tolerant pads) or the minimum of VDDIO + 2V and 3.8V (for non-5V tolerant pads). The datasheet specifies which pins can be used as 5V tolerant pins. -
Page 879: Em4 Wake-Up
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.2 EM4 Wake-up It is possible to trigger a wake-up from EM4 using any of the selectable EM4WU GPIO pins. The wake-up request can be triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the pin, the input filter is enabled during EM4. -
Page 880: Alternate Functions
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.4 Alternate Functions Alternate functions are connections to pins from peripherals, i.e. Timers, USARTs, etc.. These peripherals contain route registers, where the pin connections are enabled. In addition, the route registers contain a location bit field that configures which pin an output of that peripheral will be connected to if enabled. -
Page 881: Edge Interrupt Generation
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.5.1 Edge Interrupt Generation The GPIO can generate an interrupt from any edge of the input of any GPIO pin on the device. The edge interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM3 Stop, see Figure 26.6 Pin n Interrupt Generation on page... -
Page 882: Level Interrupt Generation
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.3.5.2 Level Interrupt Generation GPIO can generate a level interrupt using the input of any GPIO EM4 wake-up pins on the device. The interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM4. -
Page 883: Register Map
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL Port Control Register 0x004 GPIO_PA_MODEL Port Pin Mode Low Register 0x008 GPIO_PA_MODEH... - Page 884 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x42C GPIO_EM4WUEN EM4 wake up Enable Register 0x440 GPIO_ROUTEPEN I/O Routing Pin Enable Register 0x444 GPIO_ROUTELOC0 I/O Routing Location Register 0x450 GPIO_INSENSE Input Sense Register 0x454 GPIO_LOCK Configuration Lock Register silabs.com | Smart.
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Page 885: Register Description
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5 Register Description 26.5.1 GPIO_Px_CTRL - Port Control Register Offset Bit Position 0x000 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 884... - Page 886 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DINDISALT Alternate Data In Disable Data input disable for port pins using alternate modes.
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Page 887: Gpio_Px_Model - Port Pin Mode Low Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register Offset Bit Position 0x004 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 886... - Page 888 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:28 MODE7 Pin 7 Mode Configure mode for pin 7. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled.
- Page 889 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup WIREDANDALTPUL- Open-drain output uisng alternate control with filter and pullup...
- Page 890 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER WIREDANDALT Open-drain output using alternate control...
- Page 891 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULL Input enabled. DOUT determines pull direction INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction PUSHPULL Push-pull output PUSHPULLALT Push-pull using alternate control WIREDOR Wired-or output WIREDORPULLDOWN Wired-or output with pull-down...
- Page 892 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description MODE0 Pin 0 Mode Configure mode for pin 0. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled.
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Page 893: Gpio_Px_Modeh - Port Pin Mode High Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Offset Bit Position 0x008 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 892... - Page 894 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:28 MODE15 Pin 15 Mode Configure mode for pin 15. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled.
- Page 895 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALT Open-drain output using alternate control WIREDANDALTFILTER Open-drain output using alternate control with filter WIREDANDALTPULL- Open-drain output using alternate control with pullup WIREDANDALTPUL- Open-drain output uisng alternate control with filter and pullup...
- Page 896 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDORPULLDOWN Wired-or output with pull-down WIREDAND Open-drain output WIREDANDFILTER Open-drain output with filter WIREDANDPULLUP Open-drain output with pullup WIREDANDPULLUP- Open-drain output with filter and pullup FILTER WIREDANDALT Open-drain output using alternate control...
- Page 897 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULL Input enabled. DOUT determines pull direction INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction PUSHPULL Push-pull output PUSHPULLALT Push-pull using alternate control WIREDOR Wired-or output WIREDORPULLDOWN Wired-or output with pull-down...
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Page 898: Gpio_Px_Dout - Port Data Out Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description MODE8 Pin 8 Mode Configure mode for pin 8. Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set INPUTPULL Input enabled. -
Page 899: Gpio_Px_Douttgl - Port Data Out Toggle Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.5 GPIO_Px_DOUTTGL - Port Data Out Toggle Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 900: Gpio_Px_Pinlockn - Port Unlocked Pins Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.7 GPIO_Px_PINLOCKN - Port Unlocked Pins Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 901: Gpio_Extipsell - External Interrupt Port Select Low Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.9 GPIO_EXTIPSELL - External Interrupt Port Select Low Register Offset Bit Position 0x400 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 900... - Page 902 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:28 EXTIPSEL7 External Interrupt 7 Port Select Select input port for external interrupt 7. Value Mode Description PORTA Port A group selected for external interrupt 7 PORTB Port B group selected for external interrupt 7...
- Page 903 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PORTA Port A group selected for external interrupt 3 PORTB Port B group selected for external interrupt 3 PORTC Port C group selected for external interrupt 3 PORTD...
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Page 904: Gpio_Extipselh - External Interrupt Port Select High Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.10 GPIO_EXTIPSELH - External Interrupt Port Select High Register Offset Bit Position 0x404 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 903... - Page 905 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:28 EXTIPSEL15 External Interrupt 15 Port Select Select input port for external interrupt 15. Value Mode Description PORTA Port A group selected for external interrupt 15 PORTB Port B group selected for external interrupt 15...
- Page 906 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PORTA Port A group selected for external interrupt 11 PORTB Port B group selected for external interrupt 11 PORTC Port C group selected for external interrupt 11 PORTD...
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Page 907: Gpio_Extipinsell - External Interrupt Pin Select Low Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.11 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register Offset Bit Position 0x408 Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 906... - Page 908 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28 EXTIPINSEL7 External Interrupt 7 Pin Select Select the pin for external interrupt 7.
- Page 909 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:12 EXTIPINSEL3 External Interrupt 3 Pin Select Select the pin for external interrupt 3.
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Page 910: Gpio_Extipinselh - External Interrupt Pin Select High Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.12 GPIO_EXTIPINSELH - External Interrupt Pin Select High Register Offset Bit Position 0x40C Reset Access Name silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 909... - Page 911 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28 EXTIPINSEL15 External Interrupt 15 Pin Select Select the pin for external interrupt 15.
- Page 912 EFM32JG1 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:12 EXTIPINSEL11 External Interrupt 11 Pin Select Select the pin for external interrupt 11.
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Page 913: Gpio_Extirise - External Interrupt Rising Edge Trigger Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.13 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register Offset Bit Position 0x410 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 914: Gpio_Extilevel - External Interrupt Level Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.15 GPIO_EXTILEVEL - External Interrupt Level Register Offset Bit Position 0x418 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 915: Gpio_If - Interrupt Flag Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.16 GPIO_IF - Interrupt Flag Register Offset Bit Position 0x41C Reset Access Name Name Reset Access Description 31:16 EM4WU 0x0000 EM4 wake up Pin Interrupt Flag EM4 wake up Pin Interrupt flag. -
Page 916: Gpio_Ifc - Interrupt Flag Clear Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.18 GPIO_IFC - Interrupt Flag Clear Register Offset Bit Position 0x424 Reset Access Name Name Reset Access Description 31:16 EM4WU 0x0000 (R)W1 Clear EM4WU Interrupt Flag Write 1 to clear the EM4WU interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). -
Page 917: Gpio_Em4Wuen - Em4 Wake Up Enable Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.20 GPIO_EM4WUEN - EM4 wake up Enable Register Offset Bit Position 0x42C Reset Access Name Name Reset Access Description 31:16 EM4WUEN 0x0000 EM4 wake up enable Write 1 to enable EM4 wake up request, write 0 to disable EM4 wake up request. -
Page 918: Gpio_Routepen - I/O Routing Pin Enable Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.21 GPIO_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x440 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 919: Gpio_Routeloc0 - I/O Routing Location Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.22 GPIO_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x444 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 920: Gpio_Lock - Configuration Lock Register
EFM32JG1 Reference Manual GPIO - General Purpose Input/Output 26.5.24 GPIO_LOCK - Configuration Lock Register Offset Bit Position 0x454 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven-... -
Page 921: Aport - Analog Port
EFM32JG1 Reference Manual APORT - Analog Port 27. APORT - Analog Port Quick Facts What? 0 1 2 3 The Analog Port (APORT) is a set of analog buses which are used to connect I/O pins to analog periph- eral signals. -
Page 922: Functional Description
EFM32JG1 Reference Manual APORT - Analog Port 27.3 Functional Description Analog node (ANODE) 0 Analog node (ANODE) 1 Analog bus (ABUS) Analog node (ANODE) 2 Analog node (ANODE) 3 Switch control Figure 27.1. Analog Bus (ABUS) An analog bus (ABUS) consists of analog switches connected to a common wire as shown in Figure 27.1 Analog Bus (ABUS) on page... -
Page 923: Aport Abus Naming
EFM32JG1 Reference Manual APORT - Analog Port 27.3.1 APORT ABUS Naming Producer 0 (e.g. DAC) Producer 1 (e.g. DAC) Producer 2 (e.g. DAC) Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Consumer 0 (e.g. - Page 924 EFM32JG1 Reference Manual APORT - Analog Port instances of an APORT client connect to different ABUSes. For example, ACMP0 BUS1X might connect to the ABUS APAX while ACMP1 BUS1X might connect to ABUS APCX. Refer to the APORT Client Map in the device datasheet to map the generalized APORT client bus name to an actual device ABUS.
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Page 925: Managing Abuses
EFM32JG1 Reference Manual APORT - Analog Port 27.3.2 Managing ABUSes The ABUSes of an APORT are shared resources. The user needs to be mindful of this in assigning I/O for different clients throughout the chip, as it is possible to have conflicts for a given ABUS. Each ABUS has an arbiter responsible for limiting the control over the ABUS to one and only one client. - Page 926 EFM32JG1 Reference Manual APORT - Analog Port APORT_CONTROL ABUS_REQ = ABUS_REQ = ABUS_REQ = 0000_0001 0011_0000 0000_1111 ACMP0 ACMP1 ADC0 Figure 27.4. APORT Example 2: Bus Conlict Figure 27.4 APORT Example 2: Bus Conlict on page 925 is a similar example to Figure 27.3 APORT Example 1 on page...
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Page 927: Appendix 1. Abbreviations
EFM32JG1 Reference Manual Abbreviations Appendix 1. Abbreviations This section lists abbreviations used in this document. Table 1.1. Abbreviations Abbreviation Description Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architec- ture". - Page 928 EFM32JG1 Reference Manual Abbreviations Abbreviation Description Local Oscillator Non Return to Zero NVIC Nested Vector Interrupt Controller Output Feedback Mode (AES mode of operation) Power Down Peripheral Reflex System Pulse Width Modulation Random Access Memory Reset Management Unit Real Time Counter...
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Page 929: Table Of Contents
Table of Contents 1. About This Document ......1 1.1 Introduction....... 1 1.2 Conventions . - Page 930 4.7.1 CAL - CRC of DI-page and calibration temperature ....26 4.7.2 EUI48L - EUI48 OUI and Unique identifier ....27 4.7.3 EUI48H - OUI .
- Page 931 5.3.1 Debug Pins ......62 5.3.2 Debug and EM2 DeepSleep/EM3 Stop ....62 5.3.3 Authentication Access Point .
- Page 932 6.5.3 MSC_WRITECTRL - Write Control Register ....81 6.5.4 MSC_WRITECMD - Write Command Register ....82 6.5.5 MSC_ADDRB - Page Erase/Write Address Buffer .
- Page 933 7.4.1 Single Direct Register DMA Transfer ....109 7.4.2 Descriptor Linked List ......110 7.4.3 Single Descriptor Looped Transfer .
- Page 934 8.4 Registers with alternate reset......147 8.5 Register Map ......148 8.6 Register Description .
- Page 935 9.5.4 EMU_RAM0CTRL - Memory Control Register ....174 9.5.5 EMU_CMD - Command Register ..... 175 9.5.6 EMU_EM4CTRL - EM4 Control Register .
- Page 936 10.3.2.6 HFRCO and AUXHFRCO Configuration ....221 10.3.2.7 LFRCO Configuration ......221 10.3.2.8 RC Oscillator Calibration .
- Page 937 10.5.35 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register ..278 10.5.36 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) ..279 10.5.37 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) .
- Page 938 11.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) ..314 11.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) ..316 11.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) ..317 11.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) .
- Page 939 13.5.4 PRS_ROUTELOC0 - I/O Routing Location Register ....343 13.5.5 PRS_ROUTELOC1 - I/O Routing Location Register ....346 13.5.6 PRS_ROUTELOC2 - I/O Routing Location Register .
- Page 940 15. I2C - Inter-Integrated Circuit Interface ..... 395 15.1 Introduction ......395 15.2 Features .
- Page 941 15.5.3 I2Cn_STATE - State Register ..... . 426 15.5.4 I2Cn_STATUS - Status Register ..... 427 15.5.5 I2Cn_CLKDIV - Clock Division Register .
- Page 942 16.3.3.5 AUTOTX ......469 16.3.3.6 Slave Mode ......470 16.3.3.7 Synchronous Half Duplex Communication .
- Page 943 16.5.23 USARTn_I2SCTRL - I2S Control Register ....520 16.5.24 USARTn_TIMING - Timing Register ....521 16.5.25 USARTn_CTRLX - Control Register Extended .
- Page 944 17.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) ..562 17.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) ..563 17.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register ..563 17.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) .
- Page 945 18.3.3.4 Action on Fault ......600 18.3.3.5 Exiting Fault State......600 18.3.3.6 DTI Configuration Lock .
- Page 946 19.3.3.9 Debug......651 19.3.4 Underflow Output Action ......652 19.3.5 PRS Output .
- Page 947 21.1 Introduction ......687 21.2 Features ......687 21.3 Functional Description .
- Page 948 22.3.8.2 Repetitive Mode ......732 22.3.8.3 Conversion Trigger ......733 22.3.8.4 Output Results .
- Page 949 22.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register ... . 786 22.5.29 ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register ... . . 786 22.5.30 ADCn_APORTMASTERDIS - APORT Bus Master Disable Register .
- Page 950 24.5.5 GPCRC_INPUTDATA - Input 32-bit Data Register ....813 24.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register ... . 814 24.5.7 GPCRC_INPUTDATABYTE - Input 8-bit Data Register .
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Page 951: Table Of Contents
25.6.15 CRYPTO_SEQ0 - Sequence register 0 ....856 25.6.16 CRYPTO_SEQ1 - Sequence Register 1 ....857 25.6.17 CRYPTO_SEQ2 - Sequence Register 2 . - Page 952 26.3.2 EM4 Wake-up ......878 26.3.3 EM4 Retention ......878 26.3.4 Alternate Functions .
- Page 953 The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death.
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