Usb0Adr: Usb0 Indirect Address - Silicon Laboratories EFM8 Series Reference Manual

Bit Name
1
1 Dp
This bit indicates the current logic level of the D+ pin.
Value
0
1
0 Dn
This bit indicates the current logic level of the D- pin.
Value
0
1

21.4.2 USB0ADR: USB0 Indirect Address

Bit 7
Name BUSY
Access RW
Reset 0
SFR Page = ALL; SFR Address: 0xAE
Bit Name
7 BUSY
This bit is used during indirect USB0 register accesses.
6 AUTORD
This bit is used for block FIFO reads.
Value
0
1
5:0 USB0ADR
These bits hold a 6-bit address used to indirectly access the USB0 core registers. Reads and writes to USB0DAT will target
the register indicated by the USBADDR bits.
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Reset Access
DIFFERENTIAL_ONE
0 R
Name
LOW
HIGH
0 R
Name
LOW
HIGH
6 5
AUTORD
RW
0
Reset Access
0 RW
0 RW
Name
DISABLED
ENABLED
0x00 RW
Description
Differential 1 signalling on the bus.
D+ Signal Status.
Description
D+ signal currently at logic 0.
D+ signal currently at logic 1.
D- Signal Status.
Description
D- signal currently at logic 0.
D- signal currently at logic 1.
4 3
USB0ADR
RW
0x00
Description
USB0 Register Read Busy Flag.
USB0 Register Auto-Read Flag.
Description
BUSY must be written manually for each USB0 indirect register read.
The next indirect register read will automatically be initiated when firm-
ware reads USB0DAT (USBADDR bits will not be changed).
USB0 Indirect Register Address.
EFM8UB3 Reference Manual
Universal Serial Bus (USB0)
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