Configurable Logic Control Registers; Clen0: Configurable Logic Enable - Silicon Laboratories EFM8 Series Reference Manual

14.4 Configurable Logic Control Registers

14.4.1 CLEN0: Configurable Logic Enable 0

Bit 7
Name
Access
Reset
SFR Page = 0x20; SFR Address: 0xCB
Bit Name
7:4 Reserved
3 C3EN
Value
0
1
2 C2EN
Value
0
1
1 C1EN
Value
0
1
0 C0EN
Value
0
1
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6 5
Reserved
R
0x0
Reset Access Description
Must write reset value.
0 RW CLU3 Enable.
Name Description
DISABLE CLU3 is disabled. The output of the block will be logic low.
ENABLE CLU3 is enabled.
0 RW CLU2 Enable.
Name Description
DISABLE CLU2 is disabled. The output of the block will be logic low.
ENABLE CLU2 is enabled.
0 RW CLU1 Enable.
Name Description
DISABLE CLU1 is disabled. The output of the block will be logic low.
ENABLE CLU1 is enabled.
0 RW CLU0 Enable.
Name Description
DISABLE CLU0 is disabled. The output of the block will be logic low.
ENABLE CLU0 is enabled.
Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)
4 3
C3EN C2EN
RW
0
EFM8UB3 Reference Manual
2 1
C1EN
RW RW
0 0
Rev. 0.2 | 170
0
C0EN
RW
0