Figure 3 Design Flow - Microsemi SmartFusion2 Demo Manual

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory
The following figure shows the eSRAM EDAC demo operations.
Figure 3 • Design Flow
Messages from
UART Rx Interrupt
Receive UART
messages and
decode as
commands
1.Write data to address X of DDR
With EDAC enabled
2.Read back data from address X
of DDR and induce 1-bit/2bit error
3.Write data to address X of DDR
with EDAC disabled
4.Read back data from address X
of DDR with EDAC enabled
Send error detection and
correction summary to GUI
Loop
GUI
Initialize the application
EDAC loop test
1.Read data from address
specified in GUI
2.Send Error counters and
address of last error to
GUI
3.Clear status register
DG0388 Demo Guide Revision 10.0
Reset
Enable/Disable EDAC
Command for
operation?
Enable/Disable EDAC
Read/Write?
Write
Read
Write data to the
specified DDR
address
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