Altera DE2-70 User Manual page 91

hardware part is built by SOPC Builder under Quartus II. The hardware part includes all the other
blocks. The "AUDIO Controller" is a user-defined SOPC component. It is designed to send audio
data to the audio chip or receive audio data from the audio chip.
The audio chip is programmed through I2C protocol which is implemented in C code. The I2C pin
from audio chip is connected to SOPC System Interconnect Fabric through PIO controllers. In this
example, the audio chip is configured in Master Mode. The audio interface is configured as I2S and
16-bit mode. A 18.432MHz clock generated by the PLL is connected to the XTI/MCLK pin of the
audio chip through the AUDIO Controller.
50M Hz
RESE_N
Clock
to
SDRAM
SRAM
Figure 6.19. Block diagram of the audio recorder and player.
Demonstration Setup, File Locations, and Instructions
• Hardware Project directory: DE2_70_AUDIO
• Bit stream used: DE2P_TOP.sof
• Software Project directory: DE2_70_AUDIO\software\project_audio
• Software Execution File: DE2_70_AUDIO\software\project_auido\audio\debug\audio.elf
• Connect an Audio Source to the LINE-IN port of the DE2-70 board.
• Connect a Microphone to MIC-IN port on the DE2-70 board.
• Connect a speaker or headset to LINE-OUT port on the DE2-70 board.
• Load the bit stream into FPGA. (
SOPC
SDRAM
NIOS II
Controller
SRAM
Controller
JTAG
UART
PLL
Controller
SEG7
Controller
AUDIO
Controller
)
note *1
SDRAM
SRAM
LED/KEY/SW/I2C
PIO
LCD
LCD
SEG7
AUDIO
88
DE2-70 User Manual
Store
Audio
Data
Nios II
Program